Patents by Inventor Norio Nakazato
Norio Nakazato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220319751Abstract: The solenoid coil includes a coil having a first end surface and a second end surface on its both ends in an axial direction, a member which is in contact with the first end surface, and has a groove through which the wire material of the coil passes, and an insulating resin formed to coat at least an outer circumferential surface and the second end surface of the coil. The resin with a substantially U-shaped section is continuously coated on at least a part of an inner circumferential surface of the coil via an area from the outer circumferential surface to the second end surface.Type: ApplicationFiled: April 20, 2020Publication date: October 6, 2022Inventors: Yuichiro TANAKA, Shinji SETO, Norio NAKAZATO, Shunsuke MORI, Yohei KATAYAMA, Teruaki YAMANAKA, Motohiro HIRAO
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Patent number: 8547502Abstract: It is to provide a light source module capable of downsizing an edge-light type backlight in thickness and reducing the usage amount of resin. A method of manufacturing a light source module includes a process of preparing a substrate with a first reflector including a reflecting surface mounted thereon, a process of mounting a plurality of light emitting elements on the substrate, a process of mounting a wiring board having an electrode on the substrate, a process of connecting the electrode of the light emitting element and the electrode of the wiring board with metal wire, a process of mounting a second reflector having a reflecting surface on the wiring board, and a process of filling the space between the first reflector and the second reflector, with resin.Type: GrantFiled: October 21, 2008Date of Patent: October 1, 2013Assignee: Hitachi Consumer Electronics Co., Ltd.Inventors: Norio Nakazato, Kimihiko Sudo, Hiroshi Akai, Naoki Yotsumoto, Hiroshi Oyama, Shigeyuki Sasaki, Atsushi Hatakeyama, Takaaki Maruyama, Kouichi Tanabe
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Patent number: 8120070Abstract: A wiring board with an electronic device comprising a plurality of trenches arranged in parallel on a substrate, a common trench communicating the plurality of trenches with each other at one of their ends on the substrate, a metal layer formed at the bottom of the plurality of trenches, and an electrode layer connected with the metal layer and formed on a bottom of the common trench, wherein the electrode layer on the bottom of the common trench constitutes a source electrode or a drain electrode of a field effect transistor, whereby the wiring board and an electronic circuit having a good fine wire pattern and a good narrow gap between the patterns using a coating material can be formed, and a reduction for a cost of an organic thin film electronic device and the electronic circuit can be attained since they can be realized through a development of a printing technique.Type: GrantFiled: November 5, 2008Date of Patent: February 21, 2012Assignee: Hitachi, Ltd.Inventors: Norio Nakazato, Nobuo Fujieda, Masayoshi Ishibashi, Midori Kato, Tadashi Arai, Takeo Shiba
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Publication number: 20100052149Abstract: A semiconductor device includes: a die pad having a top surface; a plurality of leads arranged around the die pad; a semiconductor chip having a main surface, a back surface, and a plurality of pads formed to the main surface, and having the back surface fixedly adhered in opposing contact with the top surface of the die pad; a plurality of wires electrically connecting the plurality of pads of the semiconductor chip and the plurality of leads, respectively; and a sealing body sealing the semiconductor chip and the plurality of wires. In addition, a plurality of groove portions are formed to a chip-mounting region opposing the back surface of the semiconductor chip in the top surface of the die pad, and an adhesive for fixedly adhering the semiconductor chip to the top surface of the die pad is buried in the plurality of groove portions.Type: ApplicationFiled: August 21, 2009Publication date: March 4, 2010Inventors: Fujiaki Nose, Hiroshi Kikuchi, Norio Nakazato
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Patent number: 7671534Abstract: When a long illuminant module is constructed, debonding of a bonded interface or bending occurs due to a difference in a magnitude of thermal deformation between a lens material and a metal substrate. In an illuminant module including light emitting elements, a substrate on which the light emitting elements are mounted, a transparent encapsulating resin which encapsulates the light emitting elements, and a lens material having cavities formed therein, in which the respective light emitting elements and transparent encapsulating resin are stored, notches are formed in a surface of the lens material on the side of the substrate, and the notch surfaces of the notches and the surface of the substrate are bonded using a bonding material.Type: GrantFiled: September 27, 2006Date of Patent: March 2, 2010Assignee: Hitachi Lighting, Ltd.Inventors: Yasushi Kinoshita, Norio Nakazato, Naoki Yotsumoto, Keisuke Nishimura, Daisuke Nakahara
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Publication number: 20090114958Abstract: A wiring board with an electronic device comprising a plurality of trenches arranged in parallel on a substrate, a common trench communicating the plurality of trenches with each other at one of their ends on the substrate, a metal layer formed at the bottom of the plurality of trenches, and an electrode layer connected with the metal layer and formed on a bottom of the common trench, wherein the electrode layer on the bottom of the common trench constitutes a source electrode or a drain electrode of a field effect transistor, whereby the wiring board and an electronic circuit having a good fine wire pattern and a good narrow gap between the patterns using a coating material can be formed, and a reduction for a cost of an organic thin film electronic device and the electronic circuit can be attained since they can be realized through a development of a printing technique.Type: ApplicationFiled: November 5, 2008Publication date: May 7, 2009Inventors: Norio Nakazato, Nobuo Fujieda, Masayoshi Ishibashi, Midori Kato, Tadashi Arai, Takeo Shiba
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Patent number: 7525191Abstract: A semiconductor light source device, for enabling to cool LED elements driven with short pulses, effectively, and also being cheaply producible without increasing the number of pats thereof, comprising a plural number of light emitting diode chips 202 on a heat diffusion plate 201, and Peltier elements 208, as being thermoelectric cooling elements, for cooling the plural number of light emitting diode chips 202, wherein a pair of members 208(n) and 2008(p), building up the Peltier element for cooling each the light emitting diode chip, are electrically connected on each of the light emitting diode chip through bumps 207, so as to form said light emitting diode chip and the Peltier element as a unit on the heat diffusion plate, respectively, and thereby moving heat generation within each of the light emitting diode chips, directly, into the heat diffusion plate and/or a heat radiation plate.Type: GrantFiled: April 7, 2006Date of Patent: April 28, 2009Assignee: Hitachi, Ltd.Inventors: Norio Nakazato, Kimihiko Sudo
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Publication number: 20090103005Abstract: It is to provide a light source module capable of downsizing an edge-light type backlight in thickness and reducing the usage amount of resin. A method of manufacturing a light source module includes a process of preparing a substrate with a first reflector including a reflecting surface mounted thereon, a process of mounting a plurality of light emitting elements on the substrate, a process of mounting a wiring board having an electrode on the substrate, a process of connecting the electrode of the light emitting element and the electrode of the wiring board with metal wire, a process of mounting a second reflector having a reflecting surface on the wiring board, and a process of filling the space between the first reflector and the second reflector, with resin.Type: ApplicationFiled: October 21, 2008Publication date: April 23, 2009Inventors: Norio NAKAZATO, Kimihiko SUDO, Hiroshi Akai, Naoki Yotsumoto, Hiroshi Oyama, Shigeyuki Sasaki, Atsushi Hatakeyama, Takaaki Maruyama, Kouichi Tanabe
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Patent number: 7508054Abstract: Means for forming a package is disclosed on which is mounted a semiconductor chip with a high-speed LSI formed thereon, using a wire bonding method. The package comprises a semiconductor chip, a die pad smaller than a main surface of the semiconductor chip, a sealing member, plural leads each comprising an outer terminal portion and an inner lead portion, and plural bonding wires for connection between bonding pads formed on the semiconductor chip and the inner lead portions of the leads, each of the inner lead portions being bent in a direction away from a mounting surface of the sealing member, thereby approximating the height of the chip-side bonding pads and that of a bonding position of the inner lead portions to each other, whereby the wire length can be made shorter and it is possible to suppress an increase in inductance of the wire portions and attain impedance matching at various portion of a high-frequency signal input/output transmission path.Type: GrantFiled: June 16, 2005Date of Patent: March 24, 2009Assignee: Hitachi, Ltd.Inventors: Fujiaki Nose, Hiroshi Kikuchi, Satoshi Ueno, Norio Nakazato
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Publication number: 20070076433Abstract: When a long illuminant module is constructed, debonding of a bonded interface or bending occurs due to a difference in a magnitude of thermal deformation between a lens material and a metal substrate. In an illuminant module including light emitting elements, a substrate on which the light emitting elements are mounted, a transparent encapsulating resin which encapsulates the light emitting elements, and a lens material having cavities formed therein, in which the respective light emitting elements and transparent encapsulating resin are stored, notches are formed in a surface of the lens material on the side of the substrate, and the notch surfaces of the notches and the surface of the substrate are bonded using a bonding material.Type: ApplicationFiled: September 27, 2006Publication date: April 5, 2007Inventors: Yasushi Kinoshita, Norio Nakazato, Naoki Yotsumoto, Keisuke Nishimura, Daisuke Nakahara
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Publication number: 20060261351Abstract: A semiconductor light source device, for enabling to cool LED elements driven with short pulses, effectively, and also being cheaply producible without increasing the number of pats thereof, comprising a plural number of light emitting diode chips 202 on a heat diffusion plate 201, and Pertier elements 208, as being thermoelectric cooling elements, for cooling the plural number of light emitting diode chips 202, wherein a pair of members 208(n) and 2008(p), building up the Pertier element for cooling each the light emitting diode chip, are electrically connected on each of the light emitting diode chip through bumps 207, so as to form said light emitting diode chip and the Pertier element as a unit on the heat diffusion plate, respectively, and thereby moving heat generation within each of the light emitting diode chips, directly, into the heat diffusion plate and/or a heat radiation plate.Type: ApplicationFiled: April 7, 2006Publication date: November 23, 2006Inventors: Norio Nakazato, Kimihiko Sudo
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Publication number: 20050263869Abstract: To provide a very-low-cost and short-TAT connection structure superior in connection reliability in accordance with a method for three-dimensionally connecting a plurality of semiconductor chips at a shortest wiring length by using a through-hole electrode in order to realize a compact, high-density, and high-function semiconductor system. The back of a semiconductor chip is decreased in thickness up to a predetermined thickness through back-grinding, a hole reaching a surface-layer electrode is formed at a back position corresponding to a device-side external electrode portion through dry etching, a metallic deposit is applied to the sidewall of the hole and the circumference of the back of the hole, a metallic bump (protruded electrode) of another semiconductor chip laminated on the upper side is deformation-injected into the through-hole by compression bonding, and the metallic bump is geometrically caulked and electrically connected to the inside of a through-hole formed in an LSI chip.Type: ApplicationFiled: May 25, 2005Publication date: December 1, 2005Applicants: Renesas Technology Corp., Hitachi, Ltd.Inventors: Naotaka Tanaka, Norio Nakazato, Takahiro Naito
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Publication number: 20050233501Abstract: Means for forming a package is disclosed on which is mounted a semiconductor chip with a high-speed LSI formed thereon, using a wire bonding method. The package comprises a semiconductor chip, a die pad smaller than a main surface of the semiconductor chip, a sealing member, plural leads each comprising an outer terminal portion and an inner lead portion, and plural bonding wires for connection between bonding pads formed on the semiconductor chip and the inner lead portions of the leads, each of the inner lead portions being bent in a direction away from a mounting surface of the sealing member, thereby approximating the height of the chip-side bonding pads and that of a bonding position of the inner lead portions to each other, whereby the wire length can be made shorter and it is possible to suppress an increase in inductance of the wire portions and attain impedance matching at various portion of a high-frequency signal input/output transmission path.Type: ApplicationFiled: June 16, 2005Publication date: October 20, 2005Inventors: Fujiaki Nose, Hiroshi Kikuchi, Satoshi Ueno, Norio Nakazato
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Patent number: 6924549Abstract: Means for forming a package is disclosed on which is mounted a semiconductor chip with a high-speed LSI formed thereon, using a wire bonding method. The package comprises a semiconductor chip, a die pad smaller than a main surface of the semiconductor chip, a sealing member, plural leads each comprising an outer terminal portion and an inner lead portion, and plural bonding wires for connection between bonding pads formed on the semiconductor chip and the inner lead portions of the leads, each of the inner lead portions being bent in a direction away from a mounting surface of the sealing member, thereby approximating the height of the chip-side bonding pads and that of a bonding position of the inner lead portions to each other, whereby the wire length can be made shorter and it is possible to suppress an increase in inductance of the wire portions and attain impedance matching at various portion of a high-frequency signal input/output transmission path.Type: GrantFiled: July 18, 2003Date of Patent: August 2, 2005Assignee: Hitachi, Ltd.Inventors: Fujiaki Nose, Hiroshi Kikuchi, Satoshi Ueno, Norio Nakazato
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Patent number: 6911734Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.Type: GrantFiled: March 20, 2003Date of Patent: June 28, 2005Assignee: Hitachi, Ltd.Inventors: Hiroshi Kikuchi, Norio Nakazato, Hideko Ando, Takashi Suga, Satoru Isomura, Takashi Kubo, Hiroyasu Sasaki, Masanori Fukuhara, Naotaka Tanaka, Fujiaki Nose
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Patent number: 6911733Abstract: A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.Type: GrantFiled: February 26, 2003Date of Patent: June 28, 2005Assignee: Hitachi, Ltd.Inventors: Hiroshi Kikuchi, Norio Nakazato, Hideko Ando, Takashi Suga, Satoru Isomura, Takashi Kubo, Hiroyasu Sasaki, Masanori Fukuhara, Naotaka Tanaka, Fujiaki Nose
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Patent number: 6896405Abstract: A method of measuring a thermal resistance of laminated resin sandwiched by a first member and a second member according to the present invention includes measuring, as thermal resistance of resin, a sum of thermal resistance of an interface between the resin and the first member, thermal restistance of an interface between the resin and the second member, and thermal resistance caused by conduction of heat through the resin.Type: GrantFiled: October 7, 2002Date of Patent: May 24, 2005Assignee: Hitachi, Ltd.Inventors: Yasuo Osone, Norio Nakazato, Takashi Kubo, Masaki Asagai, Hiroshi Kikuchi
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Patent number: 6826211Abstract: Conventionally, in the wavelength locking optical system, the wavelength as detected is deviated from a targeted range owing to the change of the peripheral temperature resulting from the temperature characteristics of the wavelength error detection device. To solve this prior issue, it is arranged such that a portion of the wavelength error detection device, through which portion light-beams passes, contacts a material of high heat conductivity.Type: GrantFiled: September 20, 2001Date of Patent: November 30, 2004Assignees: Hitachi, Ltd., Opnext Japan, Inc.Inventors: Kimio Tatsuno, Katsumi Kuroguchi, Hiroaki Furuichi, Atsuhiro Yamamoto, Norio Nakazato
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Publication number: 20040214543Abstract: A microelectronic device includes a substrate, a variable capacitor including a driving mechanism for varying capacitance stored by a pair of electrodes formed in a main surface of the substrate, a plurality of fixed capacitors having fixed capacitance stored by a plurality of pairs of electrodes formed in an opposite side of the main surface, wiring for electrically connecting the variable capacitor and the fixed capacitors, and switches disposed in the main surface of the substrate to electrically connect the variable capacitor and a capacitor or capacitors selected from the plurality of fixed capacitors.Type: ApplicationFiled: February 19, 2004Publication date: October 28, 2004Inventors: Yasuo Osone, Noriyo Nishijima, Norio Nakazato
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Publication number: 20040041250Abstract: Means for forming a package is disclosed on which is mounted a semiconductor chip with a high-speed LSI formed thereon, using a wire bonding method. The package comprises a semiconductor chip, a die pad smaller than a main surface of the semiconductor chip, a sealing member, plural leads each comprising an outer terminal portion and an inner lead portion, and plural bonding wires for connection between bonding pads formed on the semiconductor chip and the inner lead portions of the leads, each of the inner lead portions being bent in a direction away from a mounting surface of the sealing member, thereby approximating the height of the chip-side bonding pads and that of a bonding position of the inner lead portions to each other, whereby the wire length can be made shorter and it is possible to suppress an increase in inductance of the wire portions and attain impedance matching at various portion of a high-frequency signal input/output transmission path.Type: ApplicationFiled: July 18, 2003Publication date: March 4, 2004Applicant: Hitachi, Ltd.Inventors: Fujiaki Nose, Hiroshi Kikuchi, Satoshi Ueno, Norio Nakazato