Abstract: A semiconductor structure includes a device region including field effect transistors located on a semiconductor substrate, and a planarization dielectric layer overlying the field effect transistors. A hydrogen-blocking structure can be formed to prevent subsequent hydrogen diffusion into the device region. A moat trench is formed through the planarization dielectric layer and into the semiconductor substrate around the device region. A ring-shaped hydrogen-diffusion-blocking material portion is formed within the moat trench. A horizontally-extending portion of a silicon nitride diffusion barrier layer is formed over the planarization dielectric layer. The ring-shaped hydrogen-diffusion-blocking material portion may include a vertically-extending annular portion of the silicon nitride layer, or may include an annular metal portion that is formed prior to formation of the silicon nitride diffusion barrier layer.

Abstract: A three-dimensional semiconductor device includes bit lines formed in the lower-interconnect-level dielectric material layers located over a substrate, bit-line-connection via structures contacting a respective one of the bit lines, pillar-shaped drain regions contacting a respective one of the bit-line-connection via structures, an alternating stack of insulating layers and electrically conductive layers located over the pillar-shaped drain regions, and memory stack structures extending through the alternating stack. A source layer overlies the alternating stack, and is electrically connected to an upper end of each vertical semiconductor channel within a subset of the vertical semiconductor channels. Vertical bit line interconnections structures extending through the levels of the alternating stack may be eliminated by forming the bit lines underneath the alternating stack, and the footprint of the layout of the three-dimensional memory device may be reduced.

Abstract: A three-dimensional semiconductor device includes bit lines formed in the lower-interconnect-level dielectric material layers located over a substrate, bit-line-connection via structures contacting a respective one of the bit lines, pillar-shaped drain regions contacting a respective one of the bit-line-connection via structures, an alternating stack of insulating layers and electrically conductive layers located over the pillar-shaped drain regions, and memory stack structures extending through the alternating stack. A source layer overlies the alternating stack, and is electrically connected to an upper end of each vertical semiconductor channel within a subset of the vertical semiconductor channels. Vertical bit line interconnections structures extending through the levels of the alternating stack may be eliminated by forming the bit lines underneath the alternating stack, and the footprint of the layout of the three-dimensional memory device may be reduced.

Abstract: A semiconductor structure includes a device region including field effect transistors located on a semiconductor substrate, and a planarization dielectric layer overlying the field effect transistors. A hydrogen-blocking structure can be formed to prevent subsequent hydrogen diffusion into the device region. A moat trench is formed through the planarization dielectric layer and into the semiconductor substrate around the device region. A ring-shaped hydrogen-diffusion-blocking material portion is formed within the moat trench. A horizontally-extending portion of a silicon nitride diffusion barrier layer is formed over the planarization dielectric layer. The ring-shaped hydrogen-diffusion-blocking material portion may include a vertically-extending annular portion of the silicon nitride layer, or may include an annular metal portion that is formed prior to formation of the silicon nitride diffusion barrier layer.

Abstract: A semiconductor structure includes a field effect transistor located on a semiconductor substrate, a silicon oxide liner contacting at least a portion of the semiconductor substrate, a silicon nitride liner contacting a top surface and a sidewall of the silicon oxide liner and contacting a top surface of the semiconductor substrate in a seal region, a silicon nitride diffusion barrier layer including a planar bottom surface that contacts top surfaces of vertically extending portions of the silicon nitride liner, and a silicon oxide material portion overlying the silicon nitride diffusion barrier layer. A combination of the silicon nitride liner and the silicon nitride diffusion barrier layer constitutes a hydrogen diffusion barrier structure that continuously extends from the seal region and over the field effect transistor.

Abstract: A stack of layers is formed that includes first, second, and third dielectric layers. Contact plugs are then formed extending through the stack. Then a fourth dielectric layer is formed over the stack and contact plugs and trenches are formed through the fourth and third dielectric layers, extending to the second dielectric layer and exposing contact plugs.

Abstract: Isolation is provided by forming a first trench, depositing a cover layer on the bottom and sidewalls of the first trench, selectively removing the cover layer from the bottom and forming a second trench extending from the bottom of the first trench. The second trench is then substantially filled by thermal oxide formed by oxidation and the first trench is subsequently filled with a deposited dielectric.

Abstract: An initial etch forms a trench over first contact areas of a plurality of NAND strings, the initial etch also forming individual openings over second contact areas of the plurality of NAND strings. Material is added in the trench to reduce an area of exposed bottom surface of the trench while maintaining the individual openings without substantial reduction of bottom surface area. Subsequent further etching extends the trench and the plurality of individual openings.

Abstract: Semiconductor fabrication techniques and associated semiconductor devices are provided in which conductive lines are separated by a low dielectric constant (low-k) material such as low-k film portions or air. An insulation layer such as SiO2 is etched to form raised structures. The structures are slimmed and a low-k material or sacrificial material is deposited. A further etching removes the material except for portions on sidewalls of the slimmed structures. A metal barrier layer and seed layer are then deposited, followed by a metal filler such as copper. Chemical mechanical polishing (CMP) removes portions of the metal above the raised structures, leaving only portions of the metal between the raised structures as spaced apart conductive lines. The sacrificial material can be removed by a thermal process, leaving air gaps. The raised structures provide strength while the air gap or other low-k material reduces capacitance.

Abstract: A wide trench having a width W1 and narrow trenches having a width W2 that is less than W1 are formed in a dielectric layer, the wide trench extending deeper in outer regions than in a central region. A trench modification step changes the width of the wide trench and reduces a depth difference between the outer regions and the central region of the wide trench.

Abstract: A wide trench having a width W1 and narrow trenches having a width W2 that is less than W1 are formed in a dielectric layer, the wide trench extending deeper in outer regions than in a central region. A trench modification step changes the width of the wide trench and reduces a depth difference between the outer regions and the central region of the wide trench.

Abstract: An integrated circuit connection structure includes a contact plug extending vertically in a first dielectric, a conductive line formed of a metal extending horizontally in the first dielectric, and a contact plug extension that extends between a top surface of the contact plug and the conductive line. The plug extension is formed of the metal, has a bottom surface that lies in contact with the top surface of the contact plug, and is bounded on at least one side by a portion of a second dielectric material.

Abstract: Dummy bit lines of are formed in a sacrificial layer at locations where bit lines are to be formed, with bit lines separated by trenches that extend through the sacrificial layer. Enclosed air gap structures are formed in the trenches between the dummy bit lines. Subsequently, the dummy bit lines are replaced with metal to form bit lines.

Abstract: An initial etch forms a trench over first contact areas of a plurality of NAND strings, the initial etch also forming individual openings over second contact areas of the plurality of NAND strings. Material is added in the trench to reduce an area of exposed bottom surface of the trench while maintaining the individual openings without substantial reduction of bottom surface area. Subsequent further etching extends the trench and the plurality of individual openings.

Abstract: Wide and narrow mandrels that are used to form sidewall spacers for patterning are formed in a sacrificial layer with openings in wide mandrels near sides of the wide mandrels. Sidewall spacers are formed on the sides of mandrels and the sacrificial layer is removed. The sidewall spacers are then used for patterning of underlying layers.

Abstract: Semiconductor fabrication techniques and associated semiconductor devices are provided in which conductive lines are separated by a low dielectric constant (low-k) material such as low-k film portions or air. An insulation layer such as SiO2 is etched to form raised structures. The structures are slimmed and a low-k material or sacrificial material is deposited. A further etching removes the material except for portions on sidewalls of the slimmed structures. A metal barrier layer and seed layer are then deposited, followed by a metal filler such as copper. Chemical mechanical polishing (CMP) removes portions of the metal above the raised structures, leaving only portions of the metal between the raised structures as spaced apart conductive lines. The sacrificial material can be removed by a thermal process, leaving air gaps. The raised structures provide strength while the air gap or other low-k material reduces capacitance.

Abstract: Semiconductor fabrication techniques and associated semiconductor devices are provided in which conductive lines are separated by a low dielectric constant (low-k) material such as low-k film portions or air. An insulation layer such as SiO2 is etched to form raised structures. The structures are slimmed and a low-k material or sacrificial material is deposited. A further etching removes the material except for portions on sidewalls of the slimmed structures. A metal barrier layer and seed layer are then deposited, followed by a metal filler such as copper. Chemical mechanical polishing (CMP) removes portions of the metal above the raised structures, leaving only portions of the metal between the raised structures as spaced apart conductive lines. The sacrificial material can be removed by a thermal process, leaving air gaps. The raised structures provide strength while the air gap or other low-k material reduces capacitance.

Abstract: Trenches are formed partially through a sacrificial layer at locations where bit lines are to be formed with some sacrificial material overlying vias. The trenches are lined with a protective layer and then the trenches are extended to expose vias. Bit lines are formed. Then sacrificial material is removed from between bit lines while portions of the protective layer remain to protect the bit lines.

Abstract: An NBTI malfunction of a P-channel MOS transistor is prevented. A semiconductor integrated circuit device includes a reset pulse control unit RPC. The reset pulse control unit RPC generates a reset pulse RP for recovery from degradation caused by NBTI of a MOS transistor that receives a negative voltage at the gate of the transistor in a standby status. After the generated reset pulse RP is inputted to the gate of the MOS transistor, an action control signal ACC for activating the MOS transistor is inputted to the gate of the MOS transistor to activate the transistor.

Abstract: A first depression and a second depression are formed in an upper surface of a first metal layer. A dielectric layer is formed over the first metal layer. Subsequently, a wide trench is formed in the dielectric layer, the wide trench extending deeper in a first outer region and in a second outer region than in a central region located between the first outer region and the second outer region, the first outer region overlying the first depression and the second outer region overlying the second depression.