Patents by Inventor Noritaka ISHIHARA
Noritaka ISHIHARA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20210126130Abstract: A semiconductor device with favorable reliability is provided. The semiconductor device includes a first insulator; a second insulator positioned over the first insulator; an oxide positioned over the second insulator; a first conductor and a second conductor positioned apart from each other over the oxide; a third insulator positioned over the oxide, the first conductor, and the second conductor; a third conductor positioned over the third insulator and at least partly overlapping with a region between the first conductor and the second conductor; a fourth insulator positioned to cover the oxide, the first conductor, the second conductor, the third insulator, and the third conductor; a fifth insulator positioned over the fourth insulator; and a sixth insulator positioned over the fifth insulator.Type: ApplicationFiled: August 24, 2018Publication date: April 29, 2021Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Yoshinobu ASAMI, Takahisa ISHIYAMA, Motomu KURATA, Ryo TOKUMARU, Noritaka ISHIHARA, Yusuke NONAKA
-
Publication number: 20210082920Abstract: A semiconductor device having high operation frequency is provided. The semiconductor device includes a transistor including a first conductive layer, a first insulating layer, a second insulating layer, a first oxide, a second oxide, a third oxide, a third insulating layer, and a second conductive layer that are stacked in this order, and a fourth insulating layer. The first conductive layer and the second conductive layer include a region overlapping with the second oxide. In a channel width direction of the transistor, a level of the bottom surface of the second oxide is from more than or equal to ?5 nm to less than 0 nm when a level of a region of the bottom surface of the second conductive layer which does not overlap with the second oxide is regarded as a reference.Type: ApplicationFiled: January 15, 2019Publication date: March 18, 2021Inventors: Yusuke NONAKA, Noritaka ISHIHARA, Tomoki HIRAMATSU, Ryunosuke HONDA, Tomoyo KAMOGAWA, Ryota HODO, Katsuaki TOCHIBAYASHI, Shunpei YAMAZAKI
-
Patent number: 10910388Abstract: According to one embodiment, a semiconductor storage device includes a first charge storage part, a first insulating part, a second charge storage part, a second insulating part, a first select transistor, and a hollow part. The first charge storage part is at a first position separated from a surface of a substrate by a first distance in a third direction. The first select transistor is at a second position separated from the surface of the substrate by a second distance in the third direction. The second distance is greater than the first distance. The hollow part is up to a third position in the third direction separated from the surface of the substrate by a third distance in the third direction. The third distance is greater than or equal to the first distance and shorter than or equal to the second distance.Type: GrantFiled: July 22, 2019Date of Patent: February 2, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Natsuki Fukuda, Satoshi Nagashima, Tetsu Morooka, Noritaka Ishihara
-
Patent number: 10892282Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.Type: GrantFiled: July 2, 2018Date of Patent: January 12, 2021Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masahiro Takahashi, Takuya Hirohashi, Masashi Tsubuku, Noritaka Ishihara, Masashi Oota
-
Publication number: 20200286902Abstract: According to one embodiment, a semiconductor storage device includes a first charge storage part, a first insulating part, a second charge storage part, a second insulating part, a first select transistor, and a hollow part. The first charge storage part is at a first position separated from a surface of a substrate by a first distance in a third direction. The first select transistor is at a second position separated from the surface of the substrate by a second distance in the third direction. The second distance is greater than the first distance. The hollow part is up to a third position in the third direction separated from the surface of the substrate by a third distance in the third direction. The third distance is greater than or equal to the first distance and shorter than or equal to the second distance.Type: ApplicationFiled: July 22, 2019Publication date: September 10, 2020Applicant: Toshiba Memory CorporationInventors: Natsuki FUKUDA, Satoshi NAGASHIMA, Tetsu MOROOKA, Noritaka ISHIHARA
-
Publication number: 20200266281Abstract: A highly reliable semiconductor device is provided. The semiconductor device includes a first insulator; a first oxide provided over the first insulator; a second oxide provided over the first oxide; a first conductor and a second conductor provided apart from each other over the second oxide; a third oxide provided over the second oxide, the first conductor, and the second conductor; a second insulating film provided over the third oxide; and a third conductor provided over the second oxide with the third oxide and the second insulating film positioned therebetween. The third oxide contains a metal element and nitrogen, and the metal element is bonded to nitrogen.Type: ApplicationFiled: October 29, 2018Publication date: August 20, 2020Inventors: Shunpei YAMAZAKI, Tomoki HIRAMATSU, Yusuke NONAKA, Noritaka ISHIHARA, Shota SAMBONSUGE, Yasumasa YAMANE, Yuta ENDO
-
Publication number: 20200266289Abstract: A semiconductor device with favorable electrical characteristics and reliability is provided. A first insulator is formed. A second insulator is formed over the first insulator. An island-shaped oxide is formed over the second insulator. A stacked body of a third insulator and a conductor is formed over the oxide. The resistance of the oxide is selectively reduced by forming a film containing a metal element over the oxide and the stacked body. After a fourth insulator is formed over the second insulator, the oxide, and the stacked body, an opening portion exposing the second insulator is formed in the fourth insulator. A fifth insulator is formed over the second insulator and the fourth insulator. Oxygen introduction treatment is performed on the fifth insulator.Type: ApplicationFiled: August 28, 2018Publication date: August 20, 2020Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Toshihiko TAKEUCHI, Tsutomu MURAKAWA, Hiroki KOMAGATA, Naoki OKUNO, Noritaka ISHIHARA, Yusuke NONAKA
-
Patent number: 10741679Abstract: Provided is a semiconductor device having favorable reliability.Type: GrantFiled: April 9, 2018Date of Patent: August 11, 2020Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kazutaka Kuriki, Yuji Egi, Hiromi Sawai, Yusuke Nonaka, Noritaka Ishihara, Daisuke Matsubayashi
-
Publication number: 20200194310Abstract: A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.Type: ApplicationFiled: August 28, 2018Publication date: June 18, 2020Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Toshihiko TAKEUCHI, Tsutomu MURAKAWA, Hiroki KOMAGATA, Daisuke MATSUBAYASHI, Noritaka ISHIHARA, Yusuke NONAKA
-
Publication number: 20200144059Abstract: A method for manufacturing a sputtering target with which an oxide semiconductor film with a small amount of defects can be formed is provided. Alternatively, an oxide semiconductor film with a small amount of defects is formed. A method for manufacturing a sputtering target is provided, which includes the steps of: forming a polycrystalline In-M-Zn oxide (M represents a metal chosen among aluminum, titanium, gallium, yttrium, zirconium, lanthanum, cesium, neodymium, and hafnium) powder by mixing, sintering, and grinding indium oxide, an oxide of the metal, and zinc oxide; forming a mixture by mixing the polycrystalline In-M-Zn oxide powder and a zinc oxide powder; forming a compact by compacting the mixture; and sintering the compact.Type: ApplicationFiled: December 30, 2019Publication date: May 7, 2020Inventors: Shunpei YAMAZAKI, Masashi TSUBUKU, Masashi OOTA, Yoichi KUROSAWA, Noritaka ISHIHARA
-
Publication number: 20200035711Abstract: To provide a method for manufacturing a semiconductor device including an oxide semiconductor film having conductivity, or a method for manufacturing a semiconductor device including an oxide semiconductor film having a light-transmitting property and conductivity. The method for manufacturing a semiconductor device includes the steps of forming an oxide semiconductor film over a first insulating film, performing first heat treatment in an atmosphere where oxygen contained in the oxide semiconductor film is released, and performing second heat treatment in a hydrogen-containing atmosphere, so that an oxide semiconductor film having conductivity is formed.Type: ApplicationFiled: October 7, 2019Publication date: January 30, 2020Inventors: Masashi OOTA, Noritaka ISHIHARA, Motoki NAKASHIMA, Yoichi KUROSAWA, Shunpei YAMAZAKI, Yasuharu HOSAKA, Toshimitsu OBONAI, Junichi KOEZUKA
-
Patent number: 10522347Abstract: A method for manufacturing a sputtering target with which an oxide semiconductor film with a small amount of defects can be formed is provided. Alternatively, an oxide semiconductor film with a small amount of defects is formed. A method for manufacturing a sputtering target is provided, which includes the steps of: forming a polycrystalline In-M-Zn oxide (M represents a metal chosen among aluminum, titanium, gallium, yttrium, zirconium, lanthanum, cesium, neodymium, and hafnium) powder by mixing, sintering, and grinding indium oxide, an oxide of the metal, and zinc oxide; forming a mixture by mixing the polycrystalline In-M-Zn oxide powder and a zinc oxide powder; forming a compact by compacting the mixture; and sintering the compact.Type: GrantFiled: March 7, 2017Date of Patent: December 31, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Masashi Tsubuku, Masashi Oota, Yoichi Kurosawa, Noritaka Ishihara
-
Patent number: 10461099Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.Type: GrantFiled: January 25, 2018Date of Patent: October 29, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masahiro Takahashi, Takuya Hirohashi, Masashi Tsubuku, Noritaka Ishihara, Masashi Oota
-
Patent number: 10439074Abstract: A semiconductor device with improved electrical characteristics is provided. A semiconductor device with improved field effect mobility is provided. A semiconductor device in which the field-effect mobility is not lowered even at high temperatures is provided. A semiconductor device which can be formed at low temperatures is provided. A semiconductor device with improved productivity can be provided. In the semiconductor device, there is a range of a gate voltage where the field-effect mobility increases as the temperature increases within a range of the gate voltage from 0 V to 10 V. For example, such a range of a gate voltage exists at temperatures ranging from a room temperature (25° C.) to 120° C. In the semiconductor device, the off-state current is kept extremely low (lower than or equal to the detection limit of a measurement device) within the above temperature range.Type: GrantFiled: July 13, 2018Date of Patent: October 8, 2019Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kenichi Okazaki, Masashi Tsubuku, Satoru Saito, Noritaka Ishihara
-
Publication number: 20190139783Abstract: A semiconductor device having high reliability is provided.Type: ApplicationFiled: April 11, 2017Publication date: May 9, 2019Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Kazutaka KURIKI, Yuji EGI, Noritaka ISHIHARA, Yusuke NONAKA, Yasumasa YAMANE, Ryo TOKUMARU, Daisuke MATSUBAYASHI
-
Publication number: 20180337289Abstract: A semiconductor device with improved electrical characteristics is provided. A semiconductor device with improved field effect mobility is provided. A semiconductor device in which the field-effect mobility is not lowered even at high temperatures is provided. A semiconductor device which can be formed at low temperatures is provided. A semiconductor device with improved productivity can be provided. In the semiconductor device, there is a range of a gate voltage where the field-effect mobility increases as the temperature increases within a range of the gate voltage from 0 V to 10 V. For example, such a range of a gate voltage exists at temperatures ranging from a room temperature (25° C.) to 120° C. In the semiconductor device, the off-state current is kept extremely low (lower than or equal to the detection limit of a measurement device) within the above temperature range.Type: ApplicationFiled: July 13, 2018Publication date: November 22, 2018Inventors: Shunpei YAMAZAKI, Kenichi OKAZAKI, Masashi TSUBUKU, Satoru SAITO, Noritaka ISHIHARA
-
Publication number: 20180323220Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.Type: ApplicationFiled: July 2, 2018Publication date: November 8, 2018Inventors: Masahiro TAKAHASHI, Takuya HIROHASHI, Masashi TSUBUKU, Noritaka ISHIHARA, Masashi OOTA
-
Patent number: 10084096Abstract: After a sputtering gas is supplied to a deposition chamber, plasma including an ion of the sputtering gas is generated in the vicinity of a target. The ion of the sputtering gas is accelerated and collides with the target, so that flat-plate particles and atoms of the target are separated from the target. The flat-plate particles are deposited with a gap therebetween so that the flat plane faces a substrate. The atom and the aggregate of the atoms separated from the target enter the gap between the deposited flat-plate particles and grow in the plane direction of the substrate to fill the gap. A film is formed over the substrate. After the deposition, heat treatment is performed at high temperature in an oxygen atmosphere, which forms an oxide with a few oxygen vacancies and high crystallinity.Type: GrantFiled: September 7, 2017Date of Patent: September 25, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Haruyuki Baba, Akio Suzuki, Hiromi Sawai, Masahiko Hayakawa, Noritaka Ishihara, Masashi Oota
-
Publication number: 20180233588Abstract: Provided is a semiconductor device having favorable reliability.Type: ApplicationFiled: April 9, 2018Publication date: August 16, 2018Inventors: Shunpei Yamazaki, Kazutaka Kuriki, Yuji Egi, Hiromi Sawai, Yusuke Nonaka, Noritaka Ishihara, Daisuke Matsubayashi
-
Patent number: 10038100Abstract: A semiconductor device with improved electrical characteristics is provided. A semiconductor device with improved field effect mobility is provided. A semiconductor device in which the field-effect mobility is not lowered even at high temperatures is provided. A semiconductor device which can be formed at low temperatures is provided. A semiconductor device with improved productivity can be provided. In the semiconductor device, there is a range of a gate voltage where the field-effect mobility increases as the temperature increases within a range of the gate voltage from 0 V to 10 V. For example, such a range of a gate voltage exists at temperatures ranging from a room temperature (25° C.) to 120° C. In the semiconductor device, the off-state current is kept extremely low (lower than or equal to the detection limit of a measurement device) within the above temperature range.Type: GrantFiled: February 10, 2017Date of Patent: July 31, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kenichi Okazaki, Masashi Tsubuku, Satoru Saito, Noritaka Ishihara