Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.

Abstract: A semiconductor memory device includes memory cell arrays including a first memory cell and a first word line connected to the first memory cell, a first wiring electrically connected to the first word lines corresponding to the memory cell arrays, a driver circuit electrically connected to the first wiring, second wirings electrically connected to the first wiring via the driver circuit, a voltage generation circuit including output terminals disposed corresponding to the second wirings, and first circuits disposed corresponding to the memory cell arrays. The voltage generation circuit is electrically connected to the first word lines via a first current path including the second wirings, the driver circuit, and the first wiring. The voltage generation circuit is electrically connected to the first word lines via a second current path including the second wirings and the first circuits and without including the driver circuit.

Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.

Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages before a ready/busy signal changing from a ready state to a busy state.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.

Abstract: A semiconductor memory device includes memory cell arrays including a first memory cell and a first word line connected to the first memory cell, a first wiring electrically connected to the first word lines corresponding to the memory cell arrays, a driver circuit electrically connected to the first wiring, second wirings electrically connected to the first wiring via the driver circuit, a voltage generation circuit including output terminals disposed corresponding to the second wirings, and first circuits disposed corresponding to the memory cell arrays. The voltage generation circuit is electrically connected to the first word lines via a first current path including the second wirings, the driver circuit, and the first wiring. The voltage generation circuit is electrically connected to the first word lines via a second current path including the second wirings and the first circuits and without including the driver circuit.

Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages before a ready/busy signal changing from a ready state to a busy state.

Abstract: A method of controlling a memory device includes receiving an address indicating a region in a memory cell array and generating one or more voltages supplied to the memory cell array in parallel with receiving the address.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.

Abstract: A method of controlling a memory device includes receiving an address indicating a region in a memory cell array and generating one or more voltages supplied to the memory cell array in parallel with receiving the address.

Abstract: According one embodiment, a memory device includes: a memory cell array; a voltage generation circuit generating one or more voltages supplied to the memory cell array; an input/output circuit receiving an address indicating a region in the memory cell array; and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages during reception of the address.

Abstract: A semiconductor storage device includes a memory cell array, a temperature sensor configured to generate a first temperature signal corresponding to a temperature of the memory cell array in response to a first command periodically generated during a waiting period of the memory cell array, a storage circuit configured to store the first temperature signal and update the first temperature signal each time the first command is generated during the waiting period, and a voltage generation circuit configured to generate a voltage to be applied to the memory cell array based on the first temperature signal stored in the storage circuit.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including a first memory cell, a first word line, a first circuit coupled to the first word line, a first driver used for a write operation and a read operation, a second driver used for an erase operation, and a voltage generator. The first circuit includes: a second circuit capable of electrically coupling the first word line and a first interconnect; a third circuit capable of electrically coupling the first interconnect and a second interconnect; a fourth circuit capable of electrically coupling the second interconnect and the first driver in the write and read operations; and a fifth circuit capable of electrically coupling the second interconnect and the second driver in the erase operation.

Abstract: According one embodiment, a memory device includes: a memory cell array; a voltage generation circuit generating one or more voltages supplied to the memory cell array; an input/output circuit receiving an address indicating a region in the memory cell array; and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages during reception of the address.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.

Abstract: A semiconductor storage device includes a memory cell array, a temperature sensor configured to generate a first temperature signal corresponding to a temperature of the memory cell array in response to a first command periodically generated during a waiting period of the memory cell array, a storage circuit configured to store the first temperature signal and update the first temperature signal each time the first command is generated during the waiting period, and a voltage generation circuit configured to generate a voltage to be applied to the memory cell array based on the first temperature signal stored in the storage circuit.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array including a first memory cell, a first word line, a first circuit coupled to the first word line, a first driver used for a write operation and a read operation, a second driver used for an erase operation, and a voltage generator. The first circuit includes: a second circuit capable of electrically coupling the first word line and a first interconnect; a third circuit capable of electrically coupling the first interconnect and a second interconnect; a fourth circuit capable of electrically coupling the second interconnect and the first driver in the write and read operations; and a fifth circuit capable of electrically coupling the second interconnect and the second driver in the erase operation.

Abstract: A semiconductor memory device includes a plurality of blocks of memory cells, including first, second, and third blocks of a first group of blocks and fourth fifth and sixth blocks of a second group of blocks, a plurality of word lines for each of the blocks, a first decode circuit for the first group, and a second decode circuit for the second group. When the first block is selected, the first decode circuit transfers a first voltage to the word lines of the first block, transfers a second voltage lower than the first voltage to the word lines of the second block, and causes the word lines of the third block to go into an electrically floating state, and the second decode circuit causes the words lines of the fourth block, the fifth block, and the sixth block into the electrically floating state.