Patents by Inventor Noriyoshi Shimizu

Noriyoshi Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240413064
    Abstract: A wiring board includes a first insulating layer provided on an interconnect layer, a second insulating layer provided on the first insulating layer, a first opening formed in the first insulating layer and reaching the interconnect layer, a second opening formed in the second insulating layer and having a lower end connected to an upper end of the first opening, a third opening formed in the second insulating layer and having a lower end connected to an upper end of the second opening, and a connection terminal formed inside the first, second, and the third openings, and making contact with an upper surface of the interconnect layer. The lower end diameter of the second opening is equal to the upper end diameter of the first opening, and the lower end diameter of the third opening is larger than the upper end diameter of the second opening.
    Type: Application
    Filed: June 5, 2024
    Publication date: December 12, 2024
    Inventors: Takashi NISHIYAMA, Tomoo YAMASAKI, Noriyoshi SHIMIZU
  • Publication number: 20240283121
    Abstract: A waveguide substrate includes a core substrate through which first through holes and second through holes are formed, a first conductive layer covering an inner wall of the first through holes and both sides of the core substrate, a second conductive layer covering an inner wall of the second through holes and both sides of the core substrate, a first filler material filling a space surrounded by the first conductive layer inside the first through holes, a second filler material filling a space surrounded by the second conductive layer inside the second through holes, and third conductive layers disposed on respective sides of the core substrate, the third conductive layers overlapping the first and second through holes in a plan view, and the third conductive layers being electrically connected to the first and second conductive layers, wherein the second conductive layer overlaps the first through holes in the plan view.
    Type: Application
    Filed: February 8, 2024
    Publication date: August 22, 2024
    Inventors: Hiroshi TANEDA, Yoko NAKABAYASHI, Noriyoshi SHIMIZU, Noritaka KATAGIRI, Tatsuki SUMI
  • Patent number: 11792927
    Abstract: An interconnect substrate includes a core layer including a resin layer mainly composed of a non-photosensitive thermosetting resin and a through interconnect extending through the resin layer, the core layer having no reinforcement member contained therein, a first interconnect structure laminated on a first side of the core layer and including first interconnect layers and first insulating layers mainly composed of a photosensitive resin, and a second interconnect structure laminated on a second side of the core layer and including second interconnect layers and a single second insulating layer mainly composed of a photosensitive resin, wherein the first interconnect layers are electrically connected to the second interconnect layers via the through interconnect, wherein the core layer has greater rigidity than the first interconnect structure and the second interconnect structure, and wherein a thickness of the second interconnect structure is greater than a thickness of each of the first insulating layer.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: October 17, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Rie Mizutani, Noriyoshi Shimizu, Hiroshi Taneda, Masaya Takizawa, Yoshiki Akiyama
  • Patent number: 11729914
    Abstract: A wiring board includes an insulating layer, a thin film capacitor laminated on the insulating layer, an interconnect layer electrically connected to the thin film capacitor, and an encapsulating resin layer laminated on the thin film capacitor. The interconnect layer includes a pad protruding from the thin film capacitor. The encapsulating resin layer is a mold resin having a non-photosensitive thermosetting resin as a main component thereof. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: August 15, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO.. LTD.
    Inventors: Hiroshi Taneda, Noriyoshi Shimizu, Rie Mizutani, Masaya Takizawa, Yoshiki Akiyama
  • Patent number: 11716810
    Abstract: A wiring board includes a first interconnect structure including a first interconnect layer, and a first insulating layer including a non-photosensitive thermosetting resin as a main component thereof, a second interconnect structure including second interconnect layers, and second insulating layers including a photosensitive resin as a main component thereof, and laminated on the first interconnect structure, and an encapsulating resin layer including a non-photosensitive thermosetting resin as a main component thereof, and laminated on an uppermost second insulating layer. An uppermost second interconnect layer includes a pad protruding from the uppermost second insulating layer. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad. Thermal expansion coefficients of the first insulating layer and the encapsulating resin layer are lower than that of the second insulating layers.
    Type: Grant
    Filed: April 26, 2022
    Date of Patent: August 1, 2023
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Masaya Takizawa, Rie Mizutani, Hiroshi Taneda, Yoshiki Akiyama, Noriyoshi Shimizu
  • Publication number: 20230066839
    Abstract: A wiring board includes an interconnect structure including a plurality of interconnect layers, and a plurality of insulating layers having a photosensitive resin as a main component thereof, and an encapsulating resin layer having a non-photosensitive thermosetting resin as a main component thereof, laminated on an uppermost insulating layer of the plurality of insulating layers. An uppermost interconnect layer of the plurality of interconnect layers includes a pad protruding from the uppermost insulating layer. The encapsulating resin layer exposes an upper surface of the pad, and covers at least a portion of a side surface of the pad, and at least a portion of side surfaces of the plurality of insulating layers. The pad is configured to receive a semiconductor chip to be mounted thereon.
    Type: Application
    Filed: August 3, 2022
    Publication date: March 2, 2023
    Inventors: Hiroshi TANEDA, Noriyoshi SHIMIZU, Rie MIZUTANI, Masaya TAKIZAWA, Yoshiki AKIYAMA
  • Publication number: 20230054390
    Abstract: An interconnect substrate includes a core layer including a resin layer mainly composed of a non-photosensitive thermosetting resin and a through interconnect extending through the resin layer, the core layer having no reinforcement member contained therein, a first interconnect structure laminated on a first side of the core layer and including first interconnect layers and first insulating layers mainly composed of a photosensitive resin, and a second interconnect structure laminated on a second side of the core layer and including second interconnect layers and a single second insulating layer mainly composed of a photosensitive resin, wherein the first interconnect layers are electrically connected to the second interconnect layers via the through interconnect, wherein the core layer has greater rigidity than the first interconnect structure and the second interconnect structure, and wherein a thickness of the second interconnect structure is greater than a thickness of each of the first insulating layer.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 23, 2023
    Inventors: Rie MIZUTANI, Noriyoshi SHIMIZU, Hiroshi TANEDA, Masaya TAKIZAWA, Yoshiki AKIYAMA
  • Publication number: 20220361340
    Abstract: A wiring board includes an insulating layer, a thin film capacitor laminated on the insulating layer, an interconnect layer electrically connected to the thin film capacitor, and an encapsulating resin layer laminated on the thin film capacitor. The interconnect layer includes a pad protruding from the thin film capacitor. The encapsulating resin layer is a mold resin having a non-photosensitive thermosetting resin as a main component thereof. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad.
    Type: Application
    Filed: April 26, 2022
    Publication date: November 10, 2022
    Inventors: Hiroshi TANEDA, Noriyoshi SHIMIZU, Rie MIZUTANI, Masaya TAKIZAWA, Yoshiki AKIYAMA
  • Publication number: 20220361331
    Abstract: A wiring board includes a first interconnect structure including a first interconnect layer, and a first insulating layer including a non-photosensitive thermosetting resin as a main component thereof, a second interconnect structure including second interconnect layers, and second insulating layers including a photosensitive resin as a main component thereof, and laminated on the first interconnect structure, and an encapsulating resin layer including a non-photosensitive thermosetting resin as a main component thereof, and laminated on an uppermost second insulating layer. An uppermost second interconnect layer includes a pad protruding from the uppermost second insulating layer. The encapsulating resin layer exposes a top surface of the pad, and covers at least a portion of a side surface of the pad. Thermal expansion coefficients of the first insulating layer and the encapsulating resin layer are lower than that of the second insulating layers.
    Type: Application
    Filed: April 26, 2022
    Publication date: November 10, 2022
    Inventors: Masaya TAKIZAWA, Rie MIZUTANI, Hiroshi TANEDA, Yoshiki AKIYAMA, Noriyoshi SHIMIZU
  • Patent number: 11430725
    Abstract: A wiring board includes a first wiring layer formed on one surface of a core layer, a first insulating layer formed on the one surface of the core layer so as to cover the first wiring layer, a via wiring embedded in the first insulating layer, a second wiring layer formed on a first surface of the first insulating layer, and a second insulating layer thinner than the first insulating layer formed on the first surface of the first insulating layer so as to cover the second wiring layer. The first wiring layer comprises a pad and a plane layer provided around the pad. One end surface of the via wiring is exposed from the first surface of the first insulating layer and directly bonded to the second wiring layer. The other end surface of the via wiring is directly bonded to the pad in the first insulating layer.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: August 30, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi Shimizu, Wataru Kaneda, Akio Rokugawa
  • Publication number: 20210202361
    Abstract: A wiring board includes a first wiring layer formed on one surface of a core layer, a first insulating layer formed on the one surface of the core layer so as to cover the first wiring layer, a via wiring embedded in the first insulating layer, a second wiring layer formed on a first surface of the first insulating layer, and a second insulating layer thinner than the first insulating layer formed on the first surface of the first insulating layer so as to cover the second wiring layer. The first wiring layer comprises a pad and a plane layer provided around the pad. One end surface of the via wiring is exposed from the first surface of the first insulating layer and directly bonded to the second wiring layer. The other end surface of the via wiring is directly bonded to the pad in the first insulating layer.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Inventors: Noriyoshi Shimizu, Wataru Kaneda, Akio Rokugawa
  • Patent number: 11011457
    Abstract: A wiring substrate includes a first insulation layer containing insulating resin, a first through hole passing through the first insulation layer is the thickness direction, a pad formed within the first through hole, a second insulation layer containing insulating resin and laminated on a first surface of the first insulation layer, and a first wiring layer provided on the second insulation layer and connecting to the pad. A connecting surface of the pad that connects the first wiring layer includes a curved surface that curves in a protruding shape toward the first surface of the first insulation layer.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: May 18, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Koichi Nishimura, Noriyoshi Shimizu, Jun Furuichi
  • Patent number: 10993322
    Abstract: A circuit board includes: an insulating layer having at least a part formed of an insulating resin; and an electrode pad embedded in the insulating layer and having a neck formed on an outer side surface, the neck being held in contact with the insulating resin of the insulating layer. The electrode pad includes: a first conductor layer having an end surface exposed from one surface of the insulating layer; and a second conductor layer formed on the first conductor layer and having a grain boundary density different from a grain boundary density of the first conductor layer. The neck is formed in a region of the outer side surface, the region corresponding to a boundary part between the first conductor layer and the second conductor layer.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: April 27, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Keigo Sato, Hiroshi Taneda, Noriyoshi Shimizu
  • Patent number: 10978383
    Abstract: A wiring board includes a first wiring layer formed on one surface of a core layer, a first insulating layer formed on the one surface of the core layer so as to cover the first wiring layer, a via wiring embedded in the first insulating layer, a second wiring layer formed on a first surface of the first insulating layer, and a second insulating layer thinner than the first insulating layer formed on the first surface of the first insulating layer so as to cover the second wiring layer. The first wiring layer comprises a pad and a plane layer provided around the pad. One end surface of the via wiring is exposed from the first surface of the first insulating layer and directly bonded to the second wiring layer. The other end surface of the via wiring is directly bonded to the pad in the first insulating layer.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: April 13, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi Shimizu, Wataru Kaneda, Akio Rokugawa
  • Publication number: 20200373233
    Abstract: A wiring substrate includes a first insulation layer containing insulating resin, a first through hole passing through the first insulation layer is the thickness direction, a pad formed within the first through hole, a second insulation layer containing insulating resin and laminated on a first surface of the first insulation layer, and a first wiring layer provided on the second insulation layer and connecting to the pad. A connecting surface of the pad that connects the first wiring layer includes a curved surface that curves in a protruding shape toward the first surface of the first insulation layer.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 26, 2020
    Inventors: Koichi Nishimura, Noriyoshi Shimizu, Jun Furuichi
  • Publication number: 20200344879
    Abstract: A circuit board includes: an insulating layer having at least a part formed of an insulating resin; and an electrode pad embedded in the insulating layer and having a neck formed on an outer side surface, the neck being held in contact with the insulating resin of the insulating layer. The electrode pad includes: a first conductor layer having an end surface exposed from one surface of the insulating layer; and a second conductor layer formed on the first conductor layer and having a grain boundary density different from a grain boundary density of the first conductor layer. The neck is formed in a region of the outer side surface, the region corresponding to a boundary part between the first conductor layer and the second conductor layer.
    Type: Application
    Filed: April 20, 2020
    Publication date: October 29, 2020
    Inventors: Keigo Sato, Hiroshi Taneda, Noriyoshi Shimizu
  • Patent number: 10428422
    Abstract: A film-forming method for forming a film in a film-forming apparatus includes generating first gas molecular species and second gas molecular species by causing the first source gas and the second source gas accumulated in the accumulation mechanisms to pass through respective instantaneously-heating units, sharply raising partial pressure of the first gas molecular species and partial pressure of the second gas molecular species by projectingly supplying the first gas molecular species and the second gas molecular species to the reaction chamber in which the substrate has been placed, which has been depressurized, and which has a constant capacity; bringing the first gas molecular species or the second gas molecular species into reaction by alternately repeatedly guiding the first gas molecular species or the second gas molecular species to a surface of the substrate, and forming a compound film on the surface of the substrate.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: October 1, 2019
    Assignee: PHILTECH Inc.
    Inventors: Yuji Furumura, Noriyoshi Shimizu, Shinji Nishihara, Eri Haikata, Masato Ishikawa
  • Patent number: 10366949
    Abstract: A wiring substrate includes a first wiring structure and a second wiring structure. The first wiring structure includes a first insulating layer, which covers a first wiring layer, and a via wiring. A first through hole of the first insulating layer is filled with the via wiring. The second wiring structure includes a second wiring layer and a second insulating layer. The second wiring layer is formed on an upper surface of the first insulating layer and an upper end surface of the via wiring. The second wiring layer partially includes a roughened surface. The second insulating layer is stacked on the upper surface of the first insulating layer and covers the second wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The roughened surface of the second wiring layer has a smaller surface roughness than the first wiring layer.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: July 30, 2019
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Yusuke Gozu, Jun Furuichi, Akio Rokugawa, Takashi Ito
  • Patent number: 10326304
    Abstract: An operation state determination system includes a receiver, a first memory and a determiner. The determiner is configured to compare, at a prescribed determination time point, a power value stored in the first memory with a reference value to determine whether or not an electric load connected to a branch circuit is in operation, and output a signal in accordance with a determination result. The determiner is further configured to determine that the electric load is in operation at the prescribed determination time point, when a time period during which the power value is equal to or more than the reference value occurs within a comparison time in past before the prescribed determination time point.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: June 18, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Noriyoshi Shimizu, Takashi Nishiyama
  • Patent number: 10262932
    Abstract: A wiring board includes: a first wiring structure including: a first insulating layer; a first wiring layer; and a via wiring; a protective insulating layer formed on the lower surface of the first insulating layer to cover a side surface of a lower portion of the first wiring layer; and a second wiring structure having an insulating layer and a wiring layer and formed on the upper surface of the first insulating layer. The upper surface of the first insulating layer and the upper end surface of the via wiring are substantially flush with each other. A wiring density of the second wiring structure is higher than a wiring density of the first wiring structure. The reinforcing material is positioned on a side of the second wiring structure with respect to a center of the first insulating layer in the thickness direction of the first insulating layer.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: April 16, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Jun Furuichi, Noriyoshi Shimizu