Patents by Inventor Noriyoshi Shimizu

Noriyoshi Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9220167
    Abstract: A wiring substrate includes a first wiring structure, a second wiring structure stacked on an upper surface of the first wiring structure, and an outermost insulating layer stacked on a lower surface of the first wiring structure. The outermost insulating layer covers a part of a bottom wiring layer of the wiring layers forming the first wiring structure. The second wiring structure has a wiring density higher than that of the first wiring structure. A volume ratio V1/V2 is from 0.8 to 1.5, where V1 represents the volume of the wiring layers forming the entire second wiring structure, and V2 represents the volume of the bottom wiring layer in the first wiring structure.
    Type: Grant
    Filed: February 17, 2015
    Date of Patent: December 22, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Masato Tanaka, Toshinori Koyama, Akio Rokugawa
  • Publication number: 20150364405
    Abstract: A wiring substrate includes a first wiring layer including a first wiring part having a first wiring interval and a second wiring part having a second wiring interval wider than the first wiring interval, a metal plane layer formed on a portion of a first insulation layer formed on the first wiring layer, the first wiring part being located below the portion, a second insulation layer formed on the first insulation layer and the metal plane layer and having a first via hole and a second via hole, a second wiring layer formed on the second insulation layer and connected to the first wiring layer via a first via conductor formed in the first via hole, and a third wiring layer formed on the second insulation layer and connected to the metal plane layer via a second via conductor formed in the second via hole.
    Type: Application
    Filed: June 9, 2015
    Publication date: December 17, 2015
    Inventors: Yuji Kunimoto, Jun Furuichi, Noriyoshi Shimizu, Naoyuki Koizumi
  • Publication number: 20150357276
    Abstract: A wiring substrate includes a first wiring structure and a second wiring structure stacked thereon. The first wiring structure includes a first insulation layer and a via wiring extending through the first insulation layer. The second wiring structure includes a first wiring layer formed on the first insulation layer and the via wiring, and a first plane layer stacked on the first insulation layer and at least partially grid-shaped in a plan view to define second through holes. A second insulation layer is stacked on the first insulation layer to fill the second through holes and cover the first plane layer and the first wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The second through holes each include a lower open end and an upper open end having a smaller open width than the lower open end.
    Type: Application
    Filed: June 4, 2015
    Publication date: December 10, 2015
    Inventors: Noriyoshi SHIMIZU, Kiyoshi OI, Yuichiro SHIMIZU
  • Publication number: 20150315501
    Abstract: A solid gasification apparatus includes a reaction chamber thermally insulated by a heat insulating material, a heat beam fluid heat exchange apparatus that produces a first heated gas and a second heated gas, and a unit that includes a gas flow path. The unit spays the first heated gas against a material solid in a reaction chamber to heat the material solid, and, simultaneously, makes the material solid react with the first heated gas to produce a produced gas containing the element of the material solid. The unit makes a second heated gas contact and react with the produced gas.
    Type: Application
    Filed: April 6, 2015
    Publication date: November 5, 2015
    Inventors: Yuji Furumura, Naomi Mura, Shinji Nishihara, Noriyoshi Shimizu
  • Publication number: 20150305153
    Abstract: A wiring substrate includes an insulating layer, and a connection terminal formed on the insulating layer. The connection terminal includes a metal layer formed on the insulating layer and including an upper surface, a metal post formed on the upper surface of the metal layer and including upper and side surfaces, and a surface plating layer that covers the upper and side surfaces of the metal post. The metal layer includes a material that is inactive with respect to a material included in the surface plating layer. The metal layer has an upper surface edge part that is exposed at an outside from the side surface of the metal post in a plan view. The surface plating layer is formed to expose the upper surface edge part of the metal layer.
    Type: Application
    Filed: April 1, 2015
    Publication date: October 22, 2015
    Inventors: Kei IMAFUJI, Noriyoshi SHIMIZU, Kiyoshi OI, Hiromu ARISAKA
  • Patent number: 9167692
    Abstract: A wiring board includes a first via hole in a first insulating layer to expose a first wiring layer. A first via in the first via hole includes an end surface. A second wiring layer is arranged on the first insulating layer and the end surface of the first via. A second insulating layer covers the second wiring layer. A second via hole in the second insulating layer exposes the second wiring layer. A second via in the second via hole is arranged above the first via through the second wiring layer. The outer surface of the first insulating layer is lower in surface roughness than an inner surface of the first via hole.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: October 20, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Toshinori Koyama, Akio Rokugawa
  • Publication number: 20150282323
    Abstract: A wiring board includes a first wiring layer formed on one surface of a core layer, a first insulating layer formed on the one surface of the core layer so as to cover the first wiring layer, a via wiring embedded in the first insulating layer, a second wiring layer formed on a first surface of the first insulating layer, and a second insulating layer thinner than the first insulating layer formed on the first surface of the first insulating layer so as to cover the second wiring layer. The first wiring layer comprises a pad and a plane layer provided around the pad. One end surface of the via wiring is exposed from the first surface of the first insulating layer and directly bonded to the second wiring layer. The other end surface of the via wiring is directly bonded to the pad in the first insulating layer.
    Type: Application
    Filed: March 20, 2015
    Publication date: October 1, 2015
    Inventors: Noriyoshi Shimizu, Wataru Kaneda, Akio Rokugawa
  • Publication number: 20150282307
    Abstract: A wiring board includes first insulating layers; first wiring layers; first via wirings; second insulating layers; second wiring layers; second via wirings; and a solder resist layer, wherein the first insulating layers are composed of non-photosensitive resin, wherein the second insulating layers, and the solder resist layer are composed of photosensitive resin, respectively, wherein the first surface of the uppermost first insulating layer and the first end surface of the first via wiring embedded in the uppermost first insulating layer are polished surfaces, wherein the first end surface of the first via wiring embedded in the uppermost first insulating layer is flush with the first surface of the uppermost first insulating layer, and wherein the wiring density of the second wiring layers is higher than the wiring density of the first wiring layers.
    Type: Application
    Filed: February 4, 2015
    Publication date: October 1, 2015
    Inventors: Noriyoshi SHIMIZU, Shoji WATANABE, Toshinori KOYAMA, Akio ROKUGAWA
  • Patent number: 9148952
    Abstract: A wiring board includes first insulating layers and second insulating layers formed on a core layer in this order; a third insulating layer and a solder resist layer formed on another surface of the core layer in this order, first wiring layers and second wiring layers formed in the first insulating layers and the second insulating layers, respectively, wherein a first end surface of the first via wiring exposes from the first surface of the outermost first insulating layer to be directly connected with an outermost second wiring layer, the first via wiring and the outermost second wiring layer being separately formed, the first surface of the outermost first insulating layer and the first end surface of the first via wiring are polished surfaces, smooth surfaces and are flush with each other, and the wiring density of the second wiring layers is higher than that of the first wiring layers.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: September 29, 2015
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Noriyoshi Shimizu, Hitoshi Sakaguchi, Wataru Kaneda, Masato Tanaka, Akio Rokugawa
  • Publication number: 20150248153
    Abstract: An estimating apparatus includes an acquiring unit, a history recording unit, and a determining unit. The acquiring unit acquires power amounts for respective measurement times from a measuring apparatus that measures power for each branch line, as a plurality of used power amounts. The history recording unit records the plurality of used power amounts in association with dates and times. The determining unit variably sets a comparison value for comparing magnitudes of the plurality of used power amounts recorded in the history recording unit, obtains a minimum value of the comparison value in a range satisfying a condition that an amount of time for which at least some of the plurality of used power amounts are continuously equal to or below the comparison value exceeds a prescribed sustained time, and estimates the minimum value to be a peak value of stand-by power of the branch line.
    Type: Application
    Filed: August 29, 2013
    Publication date: September 3, 2015
    Inventors: Noriyoshi Shimizu, Takashi Nishiyama
  • Publication number: 20150245473
    Abstract: A wiring substrate includes a first wiring structure, a second wiring structure stacked on an upper surface of the first wiring structure, and an outermost insulating layer stacked on a lower surface of the first wiring structure. The outermost insulating layer covers a part of a bottom wiring layer of the wiring layers forming the first wiring structure. The second wiring structure has a wiring density higher than that of the first wiring structure. A volume ratio V1/V2 is from 0.8 to 1.5, where V1 represents the volume of the wiring layers forming the entire second wiring structure, and V2 represents the volume of the bottom wiring layer in the first wiring structure.
    Type: Application
    Filed: February 17, 2015
    Publication date: August 27, 2015
    Inventors: Noriyoshi SHIMIZU, Masato TANAKA, Toshinori KOYAMA, Akio ROKUGAWA
  • Patent number: 9119319
    Abstract: A wiring board includes a first insulating layer containing a thermosetting resin, a first wiring layer stacked on an upper surface of the first insulating layer, a second insulating layer stacked on the upper surface of the first insulating layer, a second wiring layer stacked on an upper surface of the second insulating layer, and a third insulating layer stacked on the upper surface of the second insulating layer. The second and third insulating layers contain a first photosensitive resin. An outer side surface of the second insulating layer is flush with an outer side surface of the first insulating layer. An outer side surface of the third insulating layer is located inside the outer side surface of the second insulating layer in a plan view. The upper surface of the second insulating layer connecting to the outer side surface thereof is exposed from the third insulating layer.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: August 25, 2015
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Wataru Kaneda, Noriyoshi Shimizu, Akio Rokugawa, Kaori Yokota
  • Publication number: 20150207074
    Abstract: A deposition method of fine particles, includes the steps of irradiating a fine particle beam formed by size-classified fine particles to an irradiated subject under a vacuum state, and depositing the fine particles on a bottom part of a groove structure formed at the irradiated subject.
    Type: Application
    Filed: March 27, 2015
    Publication date: July 23, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Yuji Awano, Noriyoshi Shimizu
  • Publication number: 20150181703
    Abstract: A wiring substrate includes first and second wiring structures. The first wiring structure includes a core substrate, first and second insulation layers formed from a thermosetting insulative resin respectively including first and second reinforcement materials, and a via wire formed in the first insulation layer. The second wiring structure includes a third insulation layer formed on an upper surface of the first insulation layer and an upper end surface of the via wire, and a wiring layer extended through the third insulation layer and electrically connected to the via wire. The outermost insulation layer, the main component of which is a photosensitive resin, is stacked on a lower surface of the second insulation layer. The second wiring structure has a higher wiring density than the first wiring structure. The first reinforcement material is partially exposed on the upper surface of the first insulation layer.
    Type: Application
    Filed: November 20, 2014
    Publication date: June 25, 2015
    Inventors: Masato TANAKA, Shoji WATANABE, Noriyoshi SHIMIZU
  • Publication number: 20150179560
    Abstract: A wiring substrate includes first and second wiring structures. The first wiring structure includes a core substrate, first and second insulation layers each formed from a thermosetting insulative resin including a reinforcement material, and a via wire formed in the first insulation layer. The second wiring structure includes a wiring layer formed on upper surfaces of the first insulation layer and the via wire, an insulation layer formed on the upper surface of the first insulation layer, and an uppermost wiring layer including a pad used to electrically connect a semiconductor chip and the wiring layer. An outermost insulation layer stacked on a lower surface of the second insulation layer exposes a portion of a lowermost wiring layer stacked on the lower surface of the second insulation layer as an external connection pad. The second wiring structure has a higher wiring density than the first wiring structure.
    Type: Application
    Filed: November 20, 2014
    Publication date: June 25, 2015
    Inventors: Hiromu Arisaka, Noriyoshi SHIMIZU, Masato TANAKA, Tetsuya KOYAMA, Akio ROKUGAWA
  • Publication number: 20150163899
    Abstract: A wiring board includes first insulating layers and second insulating layers formed on a core layer in this order; a third insulating layer and a solder resist layer formed on another surface of the core layer in this order, first wiring layers and second wiring layers formed in the first insulating layers and the second insulating layers, respectively, wherein a first end surface of the first via wiring exposes from the first surface of the outermost first insulating layer to be directly connected with an outermost second wiring layer, the first via wiring and the outermost second wiring layer being separately formed, the first surface of the outermost first insulating layer and the first end surface of the first via wiring are polished surfaces, smooth surfaces and are flush with each other, and the wiring density of the second wiring layers is higher than that of the first wiring layers.
    Type: Application
    Filed: February 19, 2015
    Publication date: June 11, 2015
    Inventors: Noriyoshi SHIMIZU, Hitoshi SAKAGUCHI, Wataru KANEDA, Masato TANAKA, Akio ROKUGAWA
  • Publication number: 20150159967
    Abstract: A small-sized fluid heating/cooling apparatus for heating or cooling a large amount of gas or liquid at a low cost. Structures where a flow passage for a fluid is formed in a heated or cooled base formed in a plate shape or a column shape, and a fluid which has passed through the narrowed flow passage impinges on a wall of a side face of the base vertically to perform heat exchange are connected in series. Heat exchange is instantaneously performed in a small space and manufacture of a mechanism performing such an operation is easy. A material constituting the flow passage may be a metal or ceramics, and a small-sized fluid heat exchanging apparatus can be manufactured at a low cost.
    Type: Application
    Filed: December 11, 2014
    Publication date: June 11, 2015
    Inventors: Yuji FURUMURA, Naomi MURA, Shinji NISHIHARA, Noriyoshi SHIMIZU
  • Patent number: 9054082
    Abstract: A semiconductor device includes a semiconductor chip, a core substrate, first and second insulating layers, and first and second wiring layers. Adhesiveness of the insulating layer to a metal is higher than adhesiveness of the core substrate to the metal. A through hole extends through the insulating layer in the thickness direction. A through via covers the hole wall surface of the through hole, extends in the thickness direction traversing the insulating layer, and electrically connects the first and second wiring layers.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: June 9, 2015
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Akio Rokugawa, Akihiko Tateiwa, Masato Tanaka
  • Publication number: 20150136370
    Abstract: In a small-sized fluid heat exchanging apparatus that heats or cools a huge amount of gas or liquid, a structure makes fluid having a high flow speed impinge perpendicularly against a wall. A flow passage is divided into a high-speed flow passage and a low-speed flow passage, and the high-speed flow passage and the low-speed flow passage are arranged so as to intersect perpendicularly with each other, according to guidelines for the shape of the flow passage. A flow passage designed according to the guidelines provides highly-efficient heat exchange.
    Type: Application
    Filed: November 11, 2014
    Publication date: May 21, 2015
    Inventors: Yuji FURUMURA, Naomi MURA, Shinji NISHIHARA, Noriyoshi SHIMIZU
  • Patent number: 9017636
    Abstract: A deposition method of fine particles, includes the steps of irradiating a fine particle beam formed by size-classified fine particles to an irradiated subject under a vacuum state, and depositing the fine particles on a bottom part of a groove structure formed at the irradiated subject.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: April 28, 2015
    Assignee: Fujitsu Limited
    Inventors: Yuji Awano, Noriyoshi Shimizu, Shintaro Sato