Patents by Inventor Noriyuki Itakura

Noriyuki Itakura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11244026
    Abstract: A computer-implemented optimization problem arithmetic method includes, receiving a combinatorial optimization problem, selecting a first arithmetic circuit from among a plurality of arithmetic circuits based on a scale or a requested accuracy of the combinatorial optimization problem and a partition mode that defines logically divided states of each of the plurality of arithmetic circuits, and causing the first arithmetic circuit to execute an arithmetic operation of the combinatorial optimization problem.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: February 8, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Hiroshi Kondou, Hiroshi Yagi, Noriyuki Itakura, Noriaki Shimada
  • Publication number: 20200089728
    Abstract: A computer-implemented optimization problem arithmetic method includes, receiving a combinatorial optimization problem, selecting a first arithmetic circuit from among a plurality of arithmetic circuits based on a scale or a requested accuracy of the combinatorial optimization problem and a partition mode that defines logically divided states of each of the plurality of arithmetic circuits, and causing the first arithmetic circuit to execute an arithmetic operation of the combinatorial optimization problem.
    Type: Application
    Filed: September 12, 2019
    Publication date: March 19, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Kondou, Hiroshi Yagi, Noriyuki Itakura, Noriaki Shimada
  • Publication number: 20200089729
    Abstract: A computer-implemented optimization problem arithmetic method includes determining, based on management information indicating a partition mode that defines a logically divided state of each of a plurality of arithmetic circuits and utilization information relating to each of the plurality of arithmetic circuits, a partition mode of each of the plurality of arithmetic circuits, receiving a combinatorial optimization problem, selecting, based on information relating to scale or requested accuracy of the combinatorial optimization problem and the determined partition mode of each of the plurality of arithmetic units, a first arithmetic circuit from among the plurality of arithmetic circuits, and causing the selected first arithmetic circuit to execute arithmetic operation of the combinatorial optimization problem based on a first partition mode determined as the partition mode of the first arithmetic circuit.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 19, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Kondou, Hiroshi Yagi, Noriyuki Itakura, Noriaki Shimada
  • Patent number: 4185877
    Abstract: A shoe for a crawler belt comprises a tray-like shoe plate, an elastic member in which fastener bushes are fitted, and a rigid tread plate affixed to one side of the elastic member. The elastic member is accommodated in the tray-like shoe plate in such a manner that the rigid tread plate is partly or wholly exposed out of the tray. The rigid tread plate and the elastic member are both detachably secured to the shoe plate by fasteners through the bushes.
    Type: Grant
    Filed: May 12, 1978
    Date of Patent: January 29, 1980
    Assignee: Mitsubishi Jukogyo Kabushiki Kaisha
    Inventors: Takakiyo Tanoue, Noriyuki Itakura