Patents by Inventor Noriyuki Itano

Noriyuki Itano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10910136
    Abstract: A semiconductor device includes an output driving circuit configured to output an output current to an output terminal; a detection resistor connected between the output terminal and the output driving circuit; an amplification unit configured to output an analog detection signal generated by amplifying a voltage between both ends of the detection resistor; a current generation circuit configured to output a reference current; a reference resistor connected between the current generation circuit and a ground and configured to output a reference voltage according to the reference current; an A/D converter configured to convert the analog detection signal into a digital detection signal using the reference voltage as a reference; and a control circuit configured to control the output current output from the output driving circuit according to the digital detection signal. The detection resistor has a same temperature characteristics as the reference resistor.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: February 2, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi Kondo, Kazuaki Kubo, Noriyuki Itano
  • Publication number: 20190080830
    Abstract: A semiconductor device includes an output driving circuit configured to output an output current to an output terminal; a detection resistor connected between the output terminal and the output driving circuit; an amplification unit configured to output an analog detection signal generated by amplifying a voltage between both ends of the detection resistor; a current generation circuit configured to output a reference current; a reference resistor connected between the current generation circuit and a ground and configured to output a reference voltage according to the reference current; an A/D converter configured to convert the analog detection signal into a digital detection signal using the reference voltage as a reference; and a control circuit configured to control the output current output from the output driving circuit according to the digital detection signal. The detection resistor has a same temperature characteristics as the reference resistor.
    Type: Application
    Filed: November 9, 2018
    Publication date: March 14, 2019
    Inventors: Satoshi Kondo, Kazuaki Kubo, Noriyuki Itano
  • Patent number: 10176913
    Abstract: An output driving circuit outputs an output current to a solenoid incorporated in a vehicle through an output terminal. A detection resistor connected between the output terminal and the output driving circuit. An amplification unit configured to output an analog detection signal generated by amplifying a voltage between both ends of the detection resistor. A current generation circuit configured to output a reference current. A reference resistor connected between the current generation circuit and a ground and configured to output a reference voltage according to the reference current. An A/D converter configured to convert the analog detection signal into a digital detection signal using the reference voltage as a reference. A control circuit configured to control the output current output from the output driving circuit according to the digital detection signal.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: January 8, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi Kondo, Kazuaki Kubo, Noriyuki Itano
  • Publication number: 20160300653
    Abstract: An output driving circuit outputs an output current to a solenoid incorporated in a vehicle through an output terminal. A detection resistor connected between the output terminal and the output driving circuit. An amplification unit configured to output an analog detection signal generated by amplifying a voltage between both ends of the detection resistor. A current generation circuit configured to output a reference current. A reference resistor connected between the current generation circuit and a ground and configured to output a reference voltage according to the reference current. An A/D converter configured to convert the analog detection signal into a digital detection signal using the reference voltage as a reference. A control circuit configured to control the output current output from the output driving circuit according to the digital detection signal.
    Type: Application
    Filed: March 15, 2016
    Publication date: October 13, 2016
    Inventors: Satoshi KONDO, Kazuaki KUBO, Noriyuki ITANO
  • Patent number: 7623397
    Abstract: A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion includes wiring connected to the pad electrodes on the semiconductor chip, mounting terminals, and a first signal path for receiving a signal output from the predetermined one of the pad electrodes and transmitting the signal to other one of the pad electrodes. The first signal path includes delay elements comparable to delays in a second signal path extending from the predetermined one of the mounting terminals to the other one of the mounting terminals through the semiconductor chip, and is disposed on a feedback path for phase comparison for synchronizing the phase of an output signal from the second signal path to the phase of an input signal to the second signal path.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: November 24, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Noriyuki Itano, Kinya Mitsumoto
  • Patent number: 7196424
    Abstract: A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion includes wiring connected to the pad electrodes on the semiconductor chip, mounting terminals, and a first signal path for receiving a signal output from the predetermined one of the pad electrodes and transmitting the signal to other one of the pad electrodes. The first signal path includes delay elements comparable to delays in a second signal path extending from the predetermined one of the mounting terminals to the other one of the mounting terminals through the semiconductor chip, and is disposed on a feedback path for phase comparison for synchronizing the phase of an output signal from the second signal path to the phase of an input signal to the second signal path.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: March 27, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Noriyuki Itano, Kinya Mitsumoto
  • Publication number: 20060284296
    Abstract: A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion includes wiring connected to the pad electrodes on the semiconductor chip, mounting terminals, and a first signal path for receiving a signal output from the predetermined one of the pad electrodes and transmitting the signal to other one of the pad electrodes. The first signal path includes delay elements comparable to delays in a second signal path extending from the predetermined one of the mounting terminals to the other one of the mounting terminals through the semiconductor chip, and is disposed on a feedback path for phase comparison for synchronizing the phase of an output signal from the second signal path to the phase of an input signal to the second signal path.
    Type: Application
    Filed: September 1, 2006
    Publication date: December 21, 2006
    Inventors: Noriyuki Itano, Kinya Mitsumoto
  • Publication number: 20050104175
    Abstract: A semiconductor device with a packaging circuit portion connected to a semiconductor chip therein. The semiconductor chip includes a plurality of pad electrodes, and the packaging circuit portion includes wiring connected to the pad electrodes on the semiconductor chip, mounting terminals, and a first signal path for receiving a signal output from the predetermined one of the pad electrodes and transmitting the signal to other one of the pad electrodes. The first signal path includes delay elements comparable to delays in a second signal path extending from the predetermined one of the mounting terminals to the other one of the mounting terminals through the semiconductor chip, and is disposed on a feedback path for phase comparison for synchronizing the phase of an output signal from the second signal path to the phase of an input signal to the second signal path.
    Type: Application
    Filed: November 8, 2004
    Publication date: May 19, 2005
    Inventors: Noriyuki Itano, Kinya Mitsumoto