Patents by Inventor Noriyuki Ito

Noriyuki Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6927950
    Abstract: A read head comprises an MR element, two bias field applying layers, and two conductive layers. The two bias field applying layers are adjacent to both side portions of the MR element, and apply a bias magnetic field to the MR element along the longitudinal direction. The two conductive layers feed a sense current to the MR element, each of the conductive layers being disposed to be adjacent to one of surfaces of each of the bias field applying layers and to overlap one of surfaces of the MR element. The conductive layers are each made of a gold alloy having a resistivity of less than 22 ??·cm and a hardness as high as or higher than the hardness of a material used for making the bias field applying layers.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: August 9, 2005
    Assignee: TDK Corporation
    Inventors: Noriyuki Ito, Kosuke Tanaka, Koichi Terunuma
  • Publication number: 20050163523
    Abstract: The invention is to provide an image heating apparatus capable of preventing an excessive temperature increase in a sheet non-passing area and a heater for use in such apparatus, and the heater for use in the image heating apparatus of the invention is constructed by including: a substrate; a heat generating resistor formed on the substrate; and first and second electrodes for supplying an electric power to the heat generating resistor; wherein each of the first and second electrodes has a first area to be contacted with a power supplying connector and a second area provided at an end portion electrically opposite to the first area, the second areas are provided along a longitudinal direction of the substrate, and the heat generating resistor is so provided as to electrically connect the second area of the first electrode and the second area of the second electrode; wherein, within the second area of the first electrode, a portion electrically closest to the first area of the first electrode is provided in th
    Type: Application
    Filed: January 21, 2005
    Publication date: July 28, 2005
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Masahito Omata, Hisashi Nakahara, Yusuke Nakazono, Satoshi Nishida, Eiji Uekawa, Isamu Takeda, Noriyuki Ito
  • Patent number: 6874137
    Abstract: A design data processing method is a method of processing hierarchically configured design data, comprises the steps of: a) obtaining first design data of a predetermined rank of hierarchy; b) obtaining second design data of a rank of hierarchy higher than the predetermined rank of hierarchy; and c) combining the second design data to the first design data.
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: March 29, 2005
    Assignee: Fujitsu Limited
    Inventors: Noriyuki Ito, Yoichiro Ishikawa, Hiroaki Hanamitsu, Ryoichi Yamashita
  • Publication number: 20040223268
    Abstract: A first and a second longitudinal bias-applying films are formed via a first mask at both sides of a magnetoresistive effective element film so that the difference in surface level between the magnetoresistive effective element film and the first and the second longitudinal bias-applying films is set within ±20 nm. Then, a first and a second electrode films are formed so as to cover edge portions of the magnetoresistive effective element film and the first and the second longitudinal bias-applying films.
    Type: Application
    Filed: April 20, 2004
    Publication date: November 11, 2004
    Applicant: TDK Corporation
    Inventors: Noriyuki Ito, Kosuke Tanaka, Koichi Terunuma
  • Publication number: 20040153988
    Abstract: A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program.
    Type: Application
    Filed: July 24, 2003
    Publication date: August 5, 2004
    Applicant: Fujitsu Limited
    Inventors: Noriyuki Ito, Ryoichi Yamashita, Keiko Osawa, Tomoyuki Isomura, Hiroaki Hanamitsu, Hideaki Katagiri
  • Publication number: 20040148582
    Abstract: A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out thereby and afterwards executes the program.
    Type: Application
    Filed: July 24, 2003
    Publication date: July 29, 2004
    Applicant: Fujitsu Limited
    Inventors: Noriyuki Ito, Ryoichi Yamashita, Keiko Osawa, Tomoyuki Isomura, Hiroaki Hanamitsu, Hideaki Katagiri
  • Patent number: 6751070
    Abstract: A first and a second longitudinal bias-applying films are formed via a first mask at both sides of a magnetoresistive effective element film so that the difference in surface level between the magnetoresistive effective element film and the first and the second longitudinal bias-applying films is set within ±20 nm. Then, a first and a second electrode films are formed so as to cover edge portions of the magnetoresistive effective element film and the first and the second longitudinal bias-applying films.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: June 15, 2004
    Assignee: TDK Corporation
    Inventors: Noriyuki Ito, Kosuke Tanaka, Koichi Terunuma
  • Publication number: 20040107563
    Abstract: A first magnetic film is formed in a primary pattern which is larger than its definitive pattern and of which edges are located within frames to be used in a frame-plating method for the second magnetic film after forming the first pole portion and the gap film. Then, the second magnetic film is formed by the frame-plating method, and the first magnetic film is etched into the definitive pattern through the second magnetic film as a mask.
    Type: Application
    Filed: December 3, 2003
    Publication date: June 10, 2004
    Applicant: TDK CORPORATION
    Inventors: Koichi Terunuma, Tetsuya Mino, Katsuya Kanakubo, Noriyuki Ito
  • Patent number: 6731474
    Abstract: Provided are a thin film magnetic head and a method of manufacturing the same, which is capable of high density recording and obtaining stable output. The thin film magnetic head includes an MR film sandwiched in between first and second shield layers. The first shield layer includes an inner layer, a magnetization stabilizing layer, an underlayer, and an outer layer laminated in order from the MR film. The second shield layer includes an inner layer, a magnetization stabilizing layer, an isolating layer, and an outer layer laminated in order from the MR film. The magnetization stabilizing layers are formed of antiferromagnetic material, so as to control the direction of magnetization of the inner layers.
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: May 4, 2004
    Assignee: TDK Corporation
    Inventors: Koichi Terunuma, Ken-ichi Takano, Noriyuki Ito
  • Patent number: 6684374
    Abstract: When a logical block is built in an LSI logic design stage, a maximum delay value between pins of a block is set based on a designer's estimation, or information of a netlist after the netlist is generated. Pins can be grouped. A delay value in a connection between pins is represented by the largest value. Additionally, a plurality of internal memory elements within a logical block are represented by one or a plurality of internal latches. Also as a delay value between a pin and an internal latch, or between an internal latch and a pin, the largest value is selected from among a plurality of delay values, and set as a representative value.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: January 27, 2004
    Assignee: Fujitsu Limited
    Inventors: Noriyuki Ito, Ryoichi Yamashita, Yoichiro Ishikawa
  • Patent number: 6678941
    Abstract: The invention is a method of manufacturing thin film magnetic heads usable for magnetic recording and reproducing drive devices such as magnetic disk drive devices. The method is characterized by forming a first magnetic film in a primary pattern which is larger than its definitive pattern and of which its edges are located within frames which are used in a frame-plating method for a second magnetic film. The second magnetic film is then formed by the frame-plating method and the first magnetic film is etched into its definitive pattern by using the second magnetic film as a mask.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: January 20, 2004
    Assignee: TDK Corporation
    Inventors: Koichi Terunuma, Tetsuya Mino, Katsuya Kanakubo, Noriyuki Ito
  • Publication number: 20040009394
    Abstract: There is provided an alkaline battery produced by sealing in an outer package body: a positive mixture containing at least one selected from manganese dioxide and a nickel oxide, a conducting agent, and an alkaline electrolytic solution (A) containing potassium hydroxide; a separator; and a negative mixture containing zinc alloy powder, a gelling agent, and an alkaline electrolytic solution (B) containing potassium hydroxide where a concentration of potassium hydroxide of the alkaline electrolytic solution (A) is 45 wt % or more, and a concentration of potassium hydroxide of the alkaline electrolytic solution (B) is 35 wt % or less. Because of this, an alkaline battery can be provided, which has desirable load characteristics, prevents the generation of gas, prevents a decrease in a storage property due to the reaction with an electrolytic solution, and has heat generation behavior suppressed at a time of occurrence of a short-circuit.
    Type: Application
    Filed: July 11, 2003
    Publication date: January 15, 2004
    Inventors: Noriyuki Ito, Minajuro Ushijima, Shinichi Iwamoto, Tetsuo Izu
  • Publication number: 20030237066
    Abstract: An electronic circuit designing method analyzes noise with respect to a wiring pair, and automatically corrects the wiring pair by determining a spacing between wirings of the wiring pair so as to prevent generation of a noise error, if the noise error is detected based on the analysis of the noise.
    Type: Application
    Filed: June 9, 2003
    Publication date: December 25, 2003
    Applicant: FUJITSU LIMITED
    Inventor: Noriyuki Ito
  • Patent number: 6664817
    Abstract: In a power supply device including a full-wave rectifying and smoothing circuit powered from a commercial AC power supply via two power supply lines, a switching regulator for separating and stepping down the output from the full-wave rectifying and smoothing circuit to output a desired DC voltage, and two capacitors after the full-wave rectifying and smoothing circuit for the terminal noise suppression purpose, a zero-cross detection circuit includes a transistor of which the emitter is connected to the low-voltage output terminal of the full-wave rectifying and smoothing circuit for outputting a zero-cross detection signal from the collector; a first resistor is connected between the base and emitter of the transistor; a second resistor is connected between one of the power supply lines and the base of the transistor; and a third resistor is connected between the other power supply line and the emitter of the transistor.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: December 16, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuhiro Nakata, Noriyuki Ito
  • Patent number: 6636392
    Abstract: A thin-film magnetic head with an MR element, includes an MR film, under films each having a multilayer structure with a first under layer and a second under layer laminated on the first under layer, and magnetic domain control films joined to side end faces of the MR film through the under films.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: October 21, 2003
    Assignee: TDK Corporation
    Inventors: Noriyuki Ito, Koichi Terunuma, Fumihiro Hiromatsu
  • Patent number: 6629305
    Abstract: A placement/net wiring processing system uses an interactive editor which eases and simplifies operations for placing or moving cells and adding, deleting or modifying wiring. The placement/net wiring processing system comprises a control means for controlling the execution of a placement and wiring operating and processing program, a display means for displaying placement and wiring information on a screen, an operating and processing means for operating the placement and wiring on the screen, and an information management means for managing the placement and wiring information. The control means copies the program read out Thereby and afterwards executes the program.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: September 30, 2003
    Assignee: Fujitsu Limited
    Inventors: Noriyuki Ito, Ryoichi Yamashita, Keiko Osawa, Tomoyuki Isomura, Hiroaki Hanamitsu, Hideaki Katagiri
  • Patent number: 6591481
    Abstract: A magnetoresistive device comprises a magnetoresistive element, two bias field applying layers that apply a longitudinal bias magnetic field to the magnetoresistive element, and two electrode layers that are located adjacent to one of the surfaces of each of the bias field applying layers and overlap one of the surfaces of the magnetoresistive element. The magnetoresistive element incorporates a protection layer located on a soft magnetic layer. A sacrificial coating layer is formed on the protection layer. Before forming the electrode layers, the coating layer and an oxide layer, formed through natural-oxidizing part of the top surface of the coating layer, are removed through etching. After the electrode layers are formed, the portion of the protection layer located in the region between the two electrode layers is oxidized, and a high resistance layer is thereby formed.
    Type: Grant
    Filed: August 3, 2001
    Date of Patent: July 15, 2003
    Assignee: TDK Corporation
    Inventors: Koji Shimazawa, Noriyuki Ito, Koichi Terunuma
  • Publication number: 20030122591
    Abstract: In a power supply device including a full-wave rectifying and smoothing circuit powered from a commercial AC power supply via two power supply lines, a switching regulator for separating and stepping down the output from the full-wave rectifying and smoothing circuit to output a desired DC voltage, and two capacitors after the full-wave rectifying and smoothing circuit for the terminal noise suppression purpose, a zero-cross detection circuit includes a transistor of which the emitter is connected to the low-voltage output terminal of the full-wave rectifying and smoothing circuit for outputting a zero-cross detection signal from the collector; a first resistor is connected between the base and emitter of the transistor; a second resistor is connected between one of the power supply lines and the base of the transistor; and a third resistor is connected between the other power supply line and the emitter of the transistor.
    Type: Application
    Filed: December 20, 2002
    Publication date: July 3, 2003
    Applicant: Canon Kabushiki Kaisha
    Inventors: Yasuhiro Nakata, Noriyuki Ito
  • Patent number: 6563681
    Abstract: A soft magnetic layer constituting a spin valve type magnetoresistance effect film comprises a multilayered body having at least two layers and including a first soft magnetic layer substantially made of Co or CoFe, and a second soft magnetic layer substantially made of NiFeX (wherein X represents at least one selected from Ta and Nb) in the order named from the side of a non-magnetic metal layer. More preferably, the soft magnetic layer comprises a multilayered body having at least three layers and including a first soft magnetic layer substantially made of Co or CoFe, a third soft magnetic layer substantially made of NiFe, and a second soft magnetic layer substantially made of NiFeX (wherein X represents at least one selected from Ta and Nb) in the order named from the side of the non-magnetic metal layer. Therefore, the detection sensitivity of a magnetic signal and the output of the magnetic head can be improved. Further, the linearity of the derived signal is also excellent.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: May 13, 2003
    Assignee: TDK Corporation
    Inventors: Tetsuro Sasaki, Koichi Terunuma, Hiroaki Kawashima, Noriyuki Ito
  • Publication number: 20030081358
    Abstract: A first and a second longitudinal bias-applying films are formed via a first mask at both sides of a magnetoresistive effective element film so that the difference in surface level between the magnetoresistive effective element film and the first and the second longitudinal bias-applying films is set within ±20 nm. Then, a first and a second electrode films are formed so as to cover edge portions of the magnetoresistive effective element film and the first and the second longitudinal bias-applying films.
    Type: Application
    Filed: May 24, 2002
    Publication date: May 1, 2003
    Applicant: TDK CORPORATION
    Inventors: Noriyuki Ito, Kosuke Tanaka, Koichi Terunuma