Patents by Inventor Noriyuki Matsubara
Noriyuki Matsubara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220308073Abstract: An object of the present invention is to provide a marker useful for early diagnosis and differentiation of Alzheimer's disease, and use thereof. An Alzheimer's disease biomarker composed of blood flotillin is provided.Type: ApplicationFiled: May 30, 2022Publication date: September 29, 2022Applicants: PUBLIC UNIVERSITY CORPORATION NAGOYA CITY UNIVERSITY, NATIONAL UNIVERSITY CORPORATION OITA UNIVERSITYInventors: Makoto Michikawa, Hiroyasu Akatsu, Mohammad Abdullah, Etsuro Matsubara, Noriyuki Kimura
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Patent number: 11422240Abstract: A light detector is provided to include a light receiving array having a plurality of light receivers respectively outputting pulse signals upon incidence of photons. A delay setting value is set which is used to adjust a time interval from when the pulse signals are output from the light receiving array to when a response number, which is a specified number of the light receivers outputting the pulse signals, is acquired.Type: GrantFiled: September 25, 2019Date of Patent: August 23, 2022Assignee: DENSO CORPORATIONInventors: Kenta Azuma, Noriyuki Ozaki, Shinji Kashiwada, Teiyu Kimura, Isamu Takai, Hiroyuki Matsubara
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Patent number: 11422241Abstract: A photodetector includes plural detectors. Each of the plural detectors has a single photon avalanche diode (hereinafter referred to as SPAD) which responds to incidence of a photon. The plural detectors include at least a first detector and a second detector. The SPAD has a recovery time period until the SPAD reaches a next photon-responsive state, in response to the SPAD responding to the incidence of the photon. The recovery time period of the SPAD in the first detector is different from the recovery time period of the SPAD in the second detector.Type: GrantFiled: September 26, 2019Date of Patent: August 23, 2022Assignee: DENSO CORPORATIONInventors: Kenta Azuma, Noriyuki Ozaki, Shinji Kashiwada, Teiyu Kimura, Isamu Takai, Hiroyuki Matsubara, Mitsuhiko Ohta, Shigeyoshi Hiratsuka
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Patent number: 11411130Abstract: A photodetector includes: a photoreceptor provided with a SPAD that is configured to respond to incidence of a photon, and as the response of the SPAD, configured to output a pulse signal; and a pulse rate control circuit configured to control sensitivity of the photoreceptor to have a pulse rate as the number of pulse signals outputted per unit time from the photoreceptor to be a set value set in advance, (i) in a set range including the set value, (ii) in a set range of the set value or more, or (iii) in a set range of the set value or less.Type: GrantFiled: October 10, 2019Date of Patent: August 9, 2022Assignee: DENSO CORPORATIONInventors: Kenta Azuma, Noriyuki Ozaki, Shinji Kashiwada, Teiyu Kimura, Isamu Takai, Hiroyuki Matsubara, Mitsuhiko Ohta, Shigeyoshi Hiratsuka
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Patent number: 11398372Abstract: A plasma processing apparatus that performs plasma processing to a substrate held on a transport carrier including a frame and a holding sheet that covers an opening of the frame includes: a transport mechanism that transports the transport carrier; a position measuring section that measures a position of the substrate to the frame; a plasma processing section that includes a plasma processing stage on which the transport carrier is loaded and a cover that covers the frame and a part of the holding sheet loaded on the plasma processing stage, and has a window section for exposing a part of the substrate; and a control section that controls the transport mechanism such that the transport carrier is loaded on the plasma processing stage to satisfy a positional relationship between the window section and the substrate based on the position information of the substrate to the frame.Type: GrantFiled: August 5, 2015Date of Patent: July 26, 2022Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shogo Okita, Hiromi Asakura, Syouzou Watanabe, Noriyuki Matsubara, Mitsuru Hiroshima, Toshihiro Wada
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Patent number: 10964597Abstract: An element chip manufacturing method including: a preparing step of preparing a first conveying carrier including a holding sheet and a frame, and a substrate held on the holding sheet, the holding sheet having a first surface and a second surface opposite the first surface, the frame attached to at least part of a peripheral edge of the holding sheet; a placing step of placing the first conveying carrier holding the substrate, on a second conveying carrier; a preprocessing step of preprocessing the substrate, after the placing step; a removing step of removing the second conveying carrier, after the preprocessing step; and a dicing step of subjecting the substrate held on the first conveying carrier to plasma exposure, after the removing step, to form a plurality of element chips from the substrate.Type: GrantFiled: September 11, 2019Date of Patent: March 30, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara, Hidefumi Saeki, Akihiro Itou
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Patent number: 10923357Abstract: Provided is a manufacturing process of an element chip, which comprises a preparation step, a setting step for setting the substrate on a stage, and a plasma-dicing step for dividing the substrate into a plurality of element chips, wherein the plasma-dicing step is achieved by repeatedly implementing etching routines each including an etching step for etching the second layer along the street regions to form a plurality of grooves and a depositing step for depositing a protective film on inner walls of the grooves, wherein the plasma-dicing step includes a first etching step for forming the grooves each having a first scallop on the inner wall thereof at a first pitch, and a second etching step for forming the grooves each having a second scallop on the inner wall thereof at a second pitch, and wherein the second pitch is greater than the first pitch.Type: GrantFiled: February 20, 2018Date of Patent: February 16, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Akihiro Itou, Atsushi Harikai, Noriyuki Matsubara, Shogo Okita
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Patent number: 10923362Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of etching regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a water-soluble first resin, water and a water-soluble organic solvent and has a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the etching regions, plasma-etching the substrate along the etching regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.Type: GrantFiled: July 27, 2020Date of Patent: February 16, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Atsushi Harikai, Noriyuki Matsubara, Shogo Okita, Hidehiko Karasaki
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Patent number: 10896849Abstract: A substrate has first and second surfaces, and includes a plurality of element regions and dividing region defining the element regions. A method for manufacturing an element chip includes: a step of spray coating, to the first surface of the substrate, a mixture containing a water-soluble resin and an organic solvent having a higher vapor pressure than water, and drying the coated mixture at a temperature of 50° C. or less, to form a protective film; a laser grooving step of removing portions of the protective film covering the dividing regions; a step of dicing the substrate into element chips by plasma etching the substrate; and a step of removing the portions of the protective film covering the element regions. The mixture has a solid component ratio of 200 g/L or more, and droplets of the sprayed mixture have an average particle size of 12 ?m or less.Type: GrantFiled: May 30, 2019Date of Patent: January 19, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidehiko Karasaki, Shogo Okita, Noriyuki Matsubara, Hidefumi Saeki
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Patent number: 10892190Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including dicing regions and element regions, attaching a holding sheet held on a frame with a die attach film in between, forming a protective film covering the substrate, forming a plurality of grooves in the protective film along the dicing regions, plasma-etching the substrate to expose the die attach film and then die attach film along the dicing regions, and picking up each of the element chips along with the separated die attach film away from the holding sheet, wherein the die attach film has an area greater than that of the substrate, and wherein the protective film includes a first covering portion covering the substrate and a second covering portion covering at least a portion of the die attach film that extends beyond an outer edge of the substrate.Type: GrantFiled: January 14, 2019Date of Patent: January 12, 2021Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shogo Okita, Atsushi Harikai, Noriyuki Matsubara, Hidefumi Saeki, Akihiro Itou
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Patent number: 10854464Abstract: A manufacturing process of an elemental chip includes steps of preparing a substrate held on the holding tape, the substrate including first and second sides opposite each other and the second side thereof being held on the holding tape, and the substrate further including a plurality of element regions and a plurality of segmentation regions defining each of the element regions; setting a nozzle to have a length between a lower most edge of the nozzle and the first side of the substrate in a range between 20 mm and 150 mm, spraying a resist solution to form droplets of the resist solution, the resist solution containing a resist constituent and a solvent; forming a resist layer by vaporizing the solvent from the droplets and depositing the resist constituent on the first side of the substrate that is held on the holding tape such that an amount of the solvent remained in the resist layer to be in a range between 5 wt. % and 20 wt.Type: GrantFiled: August 1, 2019Date of Patent: December 1, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventor: Noriyuki Matsubara
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Publication number: 20200357654Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of etching regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a water-soluble first resin, water and a water-soluble organic solvent and has a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the etching regions, plasma-etching the substrate along the etching regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.Type: ApplicationFiled: July 27, 2020Publication date: November 12, 2020Inventors: Atsushi HARIKAI, Noriyuki MATSUBARA, Shogo OKITA, Hidehiko KARASAKI
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Patent number: 10763124Abstract: A manufacturing process of an element chip comprises steps of preparing a substrate including a plurality of dicing regions and element regions each containing a plurality of convex and concave portions, holding the substrate and a frame with a holding sheet, forming a protective film by applying a first mixture to form a coated film above the substrate and by drying the coated film to form the protective film along the convex and concave portions, the first mixture containing a first resin and an organic solvent having a vapor pressure higher than water, removing the protective film by irradiating a laser beam thereon to expose the substrate in the dicing regions, plasma-etching the substrate along the dicing regions while maintaining the protective film in the element regions to individualize the substrate, and removing the protective film by contacting the protective film with an aqueous rinse solution.Type: GrantFiled: November 19, 2018Date of Patent: September 1, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Atsushi Harikai, Noriyuki Matsubara, Shogo Okita, Hidehiko Karasaki
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Patent number: 10714356Abstract: Provided is a plasma processing method which comprises steps of preparing a conveying carrier including a holding sheet and a frame provided on a peripheral region of the holding sheet, adhering the substrate on the holding sheet in an inner region inside the peripheral region to hold the substrate on the conveying carrier, sagging the holding sheet in the inner region, setting the conveying carrier on a stage provided within a plasma processing apparatus to contact the holding sheet on the stage so that the holding sheet in the inner region touches the stage before the holding sheet in the peripheral region does, and plasma processing the substrate.Type: GrantFiled: October 9, 2018Date of Patent: July 14, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shogo Okita, Atsushi Harikai, Akihiro Itou, Noriyuki Matsubara
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Patent number: 10607846Abstract: Method of manufacturing an element chip which can suppress residual debris in plasma dicing. A back surface of a semiconductor wafer is held on a dicing tape. Then, a surface of the wafer is coated with a mask that includes a water-insoluble lower mask and a water-soluble upper mask. Subsequently, an opening is formed in the mask by irradiating the mask with laser light to expose a dividing region. Then, the semiconductor wafer is caused to come into contact with water to remove the upper mask covering each of the element regions while leaving the lower layer. After that, the wafer is exposed to plasma to perform etching on the dividing region exposed from the opening until the etching reaches the back surface, thereby dicing the semiconductor wafer into a plurality of element chips. Thereafter, the lower layer mask left on the front surface of the semiconductor chips is removed.Type: GrantFiled: August 14, 2018Date of Patent: March 31, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hidehiko Karasaki, Noriyuki Matsubara, Atsushi Harikai, Hidefumi Saeki
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Publication number: 20200098636Abstract: An element chip manufacturing method including: a preparing step of preparing a first conveying carrier including a holding sheet and a frame, and a substrate held on the holding sheet, the holding sheet having a first surface and a second surface opposite the first surface, the frame attached to at least part of a peripheral edge of the holding sheet; a placing step of placing the first conveying carrier holding the substrate, on a second conveying carrier; a preprocessing step of preprocessing the substrate, after the placing step; a removing step of removing the second conveying carrier, after the preprocessing step; and a dicing step of subjecting the substrate held on the first conveying carrier to plasma exposure, after the removing step, to form a plurality of element chips from the substrate.Type: ApplicationFiled: September 11, 2019Publication date: March 26, 2020Inventors: Atsushi HARIKAI, Shogo OKITA, Noriyuki MATSUBARA, Hidefumi SAEKI, Akihiro ITOU
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Patent number: 10546783Abstract: Provided is a manufacturing process of an element chip, which comprises a preparing step for preparing a substrate containing element regions and dicing regions, a holding step for holding the substrate and a frame with a holding sheet, an applicating step for applying a resin material solution containing a resin constituent and a solvent on the substrate to form a coated layer containing the resin constituent and the solvent thereon, a heating step for heating the substrate held on the holding sheet through a heat shielding member shielding the frame and the holding sheet to substantially remove the solvent from the coated layer, thereby to form a resin layer, a patterning step for patterning the resin layer to expose the substrate in the dicing regions, and a dicing step for dicing the substrate into element chips by plasma-etching the substrate.Type: GrantFiled: June 14, 2018Date of Patent: January 28, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Noriyuki Matsubara, Hidehiko Karasaki
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Publication number: 20190371669Abstract: A substrate has first and second surfaces, and includes a plurality of element regions and dividing region defining the element regions. A method for manufacturing an element chip includes: a step of spray coating, to the first surface of the substrate, a mixture containing a water-soluble resin and an organic solvent having a higher vapor pressure than water, and drying the coated mixture at a temperature of 50° C. or less, to form a protective film; a laser grooving step of removing portions of the protective film covering the dividing regions; a step of dicing the substrate into element chips by plasma etching the substrate; and a step of removing the portions of the protective film covering the element regions. The mixture has a solid component ratio of 200 g/L or more, and droplets of the sprayed mixture have an average particle size of 12 ?m or less.Type: ApplicationFiled: May 30, 2019Publication date: December 5, 2019Inventors: Hidehiko KARASAKI, Shogo OKITA, Noriyuki MATSUBARA, Hidefumi SAEKI
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Publication number: 20190371668Abstract: A substrate has first and second surfaces, and includes a plurality of element regions and dividing region defining the element regions. An method for manufacturing an element chip includes: a protective film formation step of applying a mixture containing a water-soluble resin and a solvent to the first surface, to form a protective film; a laser grooving step of irradiating, with laser light, portions of the protective film covering the dividing regions, to remove these portions, and expose the first surface in the dividing regions; a step of dicing the substrate into element chips by plasma etching the substrate in the dividing regions; and a step of removing the portions of the protective film. The resin has melting point of 250° C. or more, or decomposition temperature of 450° C. or more, and the protective film has absorption coefficient of 1 abs·L/g·cm?1 or more for wavelength of the laser light.Type: ApplicationFiled: May 30, 2019Publication date: December 5, 2019Inventors: Hidehiko KARASAKI, Shogo OKITA, Noriyuki MATSUBARA, Atsushi HARIKAI
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Patent number: 10497622Abstract: A semiconductor chip manufacturing method includes preparing a semiconductor wafer including a front surface on which a bump is exposed, a rear surface located at a side opposite to the front surface, a plurality of element regions in each of which the bump is formed, and a dividing region defining each of the element regions, forming a mask which covers the bump and has an opening exposing the dividing region on the surface of the semiconductor wafer by spraying liquid which contains raw material of the mask along the bump by a spray coating method, and singulating the semiconductor wafer by exposing the surface of the semiconductor wafer to first plasma and etching the dividing region, which is exposed to the opening, until the rear surface is reached in a state where the bump is covered by the mask.Type: GrantFiled: June 14, 2017Date of Patent: December 3, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Shogo Okita, Mitsuru Hiroshima, Atsushi Harikai, Noriyuki Matsubara, Akihiro Itou