Patents by Inventor Noriyuki Nagai
Noriyuki Nagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240092784Abstract: A condensed heterocyclic compound has a sepiapterin reductase inhibitory action and is particularly useful for treatment of a pain. The condensed heterocyclic compound represented by Formula (I) below (R1 represents a hydrocarbon group or the like; R2 and R3 represent a hydrogen atom or the like; R4, X, and Y represent defined substituents), a tautomer or a pharmaceutically acceptable salt of the compound, or a solvate of any of these.Type: ApplicationFiled: April 13, 2021Publication date: March 21, 2024Applicants: NISSAN CHEMICAL CORPORATION, SHIONOGI & CO., LTD.Inventors: Masahiro KAMAURA, Yusuke INABA, Yusuke SHINTANI, Yuki KUWANO, Moemi NAKAO, Hiroshi NAGAI, Noriyuki KUROSE, Kenji TAKAYA, Mado NAKAJIMA
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Patent number: 11921106Abstract: A sample analyzer prepares a measurement sample from a blood sample or a body fluid sample which differs from the blood sample; measures the prepared measurement sample; obtains characteristic information representing characteristics of the components in the measurement sample; sets either a blood measurement mode for measuring the blood sample, or a body fluid measurement mode for measuring the body fluid sample as an operating mode; and measures the measurement sample prepared from the blood sample by executing operations in the blood measurement mode when the blood measurement mode has been set, and measuring the measurement sample prepared from the body fluid sample by executing operations in the body fluid measurement mode that differs from the operations in the blood measurement mode when the body fluid measurement mode has been set, is disclosed. A computer program product is also disclosed.Type: GrantFiled: February 18, 2022Date of Patent: March 5, 2024Assignee: SYSMEX CORPORATIONInventors: Takaaki Nagai, Noriyuki Narisada, Daigo Fukuma, Masanori Imazu
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Patent number: 11919548Abstract: A driving assistance device is the driving assistance device used in a vehicle capable of switching between autonomous driving and driving that requires operation by the driver, and includes a different vehicle information acquisition unit that acquires autonomous driving information on different vehicles on a traveling road of the vehicle, an autonomous driving ratio acquisition unit that acquires a ratio of autonomous driving in the different vehicles from the autonomous driving information on the different vehicles acquired by the different vehicle information acquisition unit, and a notification control unit that provides information for supporting determination on switching between autonomous driving and driving that requires operation by a driver if the ratio of autonomous driving in the different vehicles is equal to or larger than a predetermined ratio.Type: GrantFiled: August 12, 2021Date of Patent: March 5, 2024Assignee: JVCKENWOOD CorporationInventors: Ryuji Kasahara, Noriyuki Nakazawa, Hitoshi Sunohara, Katsuyuki Nagai
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Patent number: 9240391Abstract: A semiconductor device includes: a first semiconductor chip; a second semiconductor chip placed such that a front face of the second semiconductor chip faces a front face of the first semiconductor chip, and being smaller in size than the first semiconductor chip; an expansion portion extending outward from at least one side face of the second semiconductor chip; a wiring board placed such that a front face of the wiring board faces the front face of the first semiconductor chip and a back face of the second semiconductor chip; and a first interconnect formed on the back face of the second semiconductor chip and a back face of the expansion portion, and being in connection to the wiring board.Type: GrantFiled: December 26, 2013Date of Patent: January 19, 2016Assignee: Panasonic CorporationInventors: Noriyuki Nagai, Shigefumi Dohi
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Publication number: 20140103543Abstract: A semiconductor device includes: a first semiconductor chip; a second semiconductor chip placed such that a front face of the second semiconductor chip faces a front face of the first semiconductor chip, and being smaller in size than the first semiconductor chip; an expansion portion extending outward from at least one side face of the second semiconductor chip; a wiring board placed such that a front face of the wiring board faces the front face of the first semiconductor chip and a back face of the second semiconductor chip; and a first interconnect formed on the back face of the second semiconductor chip and a back face of the expansion portion, and being in connection to the wiring board.Type: ApplicationFiled: December 26, 2013Publication date: April 17, 2014Applicant: Panasonic CorporationInventors: NORIYUKI NAGAI, SHIGEFUMI DOHI
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Patent number: 8508051Abstract: A semiconductor device includes a semiconductor substrate 1, an interlayer insulating film 2, 3 formed on the semiconductor substrate 1, an electrode pad 4 formed on the interlayer insulating film 2, 3, a protective film 6 which is formed on the interlayer insulating film 2, 3 to cover a peripheral portion of the electrode pad 4, and has a first opening 5 which exposes a center portion of the electrode pad 4, a divider 7 which is formed on the electrode pad 4 exposed from the first opening 5, and divides the first opening 5 into a plurality of second openings 5d, and a barrier metal 8 formed on the protective film 6 to fill the second openings 5d. The divider 7 is interposed between the electrode pad 4 and the barrier metal 8.Type: GrantFiled: September 2, 2011Date of Patent: August 13, 2013Assignee: Panasonic CorporationInventors: Noriyuki Nagai, Kiyomi Hagihara
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Patent number: 8456024Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.Type: GrantFiled: June 5, 2012Date of Patent: June 4, 2013Assignee: Panasonic CorporationInventors: Manabu Ohnishi, Koji Takemura, Noriyuki Nagai, Hoyeun Huh, Tomoyuki Nakayama, Atsushi Doi
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Patent number: 8450734Abstract: A semiconductor device includes: a semiconductor element (1) having an internal circuit (17); and electrode pads (22, 22, . . . ) provided for the semiconductor element (1). The electrode pads (22, 22, . . . ) are electrically connected to the internal circuit (17) via control portions (31) for controlling electrical connection between the electrode pads (22, 22, . . . ) and the internal circuit (17).Type: GrantFiled: February 26, 2010Date of Patent: May 28, 2013Assignee: Panasonic CorporationInventors: Masao Takahashi, Noriyuki Nagai
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Publication number: 20120241970Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.Type: ApplicationFiled: June 5, 2012Publication date: September 27, 2012Applicant: Panasonic CorporationInventors: Manabu OHNISHI, Koji Takemura, Noriyuki Nagai, Hoyeun Huh, Tomoyuki Nakayama, Atsushi Doi
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Patent number: 8212366Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.Type: GrantFiled: October 27, 2010Date of Patent: July 3, 2012Assignee: Panasonic CorporationInventors: Manabu Ohnishi, Koji Takemura, Noriyuki Nagai, Hoyeun Huh, Tomoyuki Nakayama, Atsushi Doi
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Patent number: 8176213Abstract: A user PC 20 prepares a retrieve request by storing a SNMP command and a predetermined processing execution condition into a retrieve request of a SLP and transmits and outputs the prepared retrieve request to a printer 40 and others by multicast. Receiving the retrieve request, the printer 40 obtains and executes the SNMP command stored in the retrieve request of the SLP and processes a response to the retrieve request when the execution result meets the processing execution condition. Thus, the SNMP command is executed by receiving the retrieve request of the SLP and the response to the retrieve request of the SLP is processed corresponding to the execution result, it is not necessary to separately transmit or to obtain the request process of the SLP and the retrieve request of the SNMP through the network and the execution result of the SNMP command may be reflected to the process of the SLP.Type: GrantFiled: January 25, 2008Date of Patent: May 8, 2012Assignee: Seiko Epson CorporationInventors: Hideaki Ogata, Noriyuki Nagai
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Patent number: 8089156Abstract: The bump electrode 100 of the present invention has a structure in which dummy metals 111 are provided in the uppermost layer portion of a silicon 101 between a pad-form wiring metal 102 and a wiring metal 103 such that an edge of each dummy metal and an edge of the barrier metal 107 are not aligned in a line, and a lot of interfaces are formed between the dummy metals 111 and an interlayer film 140, and therefore expansion of a crack generated due to bump stress concentrated on the under-edge portion 109 below the barrier metal 107 between the pad-form wiring metal 102 and the wiring metal 103 is suppressed.Type: GrantFiled: September 26, 2008Date of Patent: January 3, 2012Assignee: Panasonic CorporationInventor: Noriyuki Nagai
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Publication number: 20110316153Abstract: A semiconductor device includes a semiconductor substrate 1, an interlayer insulating film 2, 3 formed on the semiconductor substrate 1, an electrode pad 4 formed on the interlayer insulating film 2, 3, a protective film 6 which is formed on the interlayer insulating film 2, 3 to cover a peripheral portion of the electrode pad 4, and has a first opening 5 which exposes a center portion of the electrode pad 4, a divider 7 which is formed on the electrode pad 4 exposed from the first opening 5, and divides the first opening 5 into a plurality of second openings 5d, and a barrier metal 8 formed on the protective film 6 to fill the second openings 5d. The divider 7 is interposed between the electrode pad 4 and the barrier metal 8.Type: ApplicationFiled: September 2, 2011Publication date: December 29, 2011Applicant: Panasonic CorporationInventors: Noriyuki NAGAI, Kiyomi Hagihara
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Patent number: 8067950Abstract: A semiconductor device in which a chip 10 is mounted on a board, includes: a pad group A provided on the chip 10 and electrically connected to an internal circuit in the chip 10; and a test pad pattern B provided on a region of the chip 10 except for a region of the chip 10 where the pad group A is provided. The pad group A includes: pads 12a formed on a principal surface of the chip 10; bumps 16a respectively formed on the pads 12a with a barrier metal layer interposed therebetween, and electrically connected to the board. The test pad pattern B includes: test pads 12b formed on the principal surface of the chip 10; test bumps 16b respectively formed on the test pads 12b with a test barrier metal layer interposed therebetween, and interconnects 11b electrically connecting adjacent ones of the test pads 12b.Type: GrantFiled: February 24, 2010Date of Patent: November 29, 2011Assignee: Panasonic CorporationInventors: Noriyuki Nagai, Takatoshi Osumi
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Publication number: 20110233772Abstract: A semiconductor element includes: a substrate having an integrated circuit; and a wire connection electrode and a bump connection electrode which are provided on a same main surface of the substrate as electrodes having a same connection function to the integrated circuit. The wire connection electrode is provided in a periphery of the main surface. The bump connection electrode is provided inside the wire connection electrode on the main surface. When a straight line dividing the main surface into two regions is determined, the wire connection electrode and the bump connection electrode are located opposite to each other with respect to the straight line.Type: ApplicationFiled: June 2, 2011Publication date: September 29, 2011Applicant: Panasonic CorporationInventors: Hiroaki FUJIMOTO, Noriyuki Nagai, Tadaaki Mimura
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Publication number: 20110215481Abstract: In a semiconductor device, a pad metal has at least a portion located immediately under a probe region, and the portion is divided into a plurality of narrow metal layers each arranged in parallel with a traveling direction of a probe. Thus, it is possible to enhance surface flatness of the pad metal and to prevent a characteristic of a semiconductor device from deteriorating without complication in processing and increase in chip size.Type: ApplicationFiled: May 12, 2011Publication date: September 8, 2011Applicant: Panasonic CorporationInventors: Noriyuki Nagai, Toshihiko Sakashita
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Patent number: 7977790Abstract: When manufacturing a semiconductor device by mounting a semiconductor chip 2 on a substrate 1 with a flip-chip method, projections 9 are formed between pads 4 arranged in multiple annular concentric layers on the semiconductor chip 2 other than pads 4 arranged along the innermost periphery thereof. On the substrate 1, bonding resin 3 is dispensed onto an area inside the innermost periphery along which the pads 4 are arranged. By heating and applying pressure, the bonding resin 3 is spread over the entire gap between the substrate 1 and the semiconductor chip 2 so as to secure the substrate 1 to the semiconductor chip 2 by the bonding resin 3, thereby preventing a void from being formed in an area outside the innermost periphery along which the pads 4 are arranged and thus stabilizing an electrical connection state between the semiconductor chip 2 and the substrate 1.Type: GrantFiled: February 18, 2009Date of Patent: July 12, 2011Assignee: Panasonic CorporationInventor: Noriyuki Nagai
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Patent number: 7944059Abstract: In a semiconductor device, a pad metal has at least a portion located immediately under a probe region, and the portion is divided into a plurality of narrow metal layers each arranged in parallel with a traveling direction of a probe. Thus, it is possible to enhance surface flatness of the pad metal and to prevent a characteristic of a semiconductor device from deteriorating without complication in processing and increase in chip size.Type: GrantFiled: July 28, 2006Date of Patent: May 17, 2011Assignee: Panasonic CorporationInventors: Noriyuki Nagai, Toshihiko Sakashita
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Publication number: 20110037173Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.Type: ApplicationFiled: October 27, 2010Publication date: February 17, 2011Applicant: PANASONIC CORPORATIONInventors: Manabu OHNISHI, Koji TAKEMURA, Noriyuki NAGAI, Hoyeun HUH, Tomoyuki NAKAYAMA, Atsushi DOI
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Patent number: 7847418Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.Type: GrantFiled: January 15, 2010Date of Patent: December 7, 2010Assignee: Panasonic CorporationInventors: Manabu Ohnishi, Koji Takemura, Noriyuki Nagai, Hoyeun Huh, Tomoyuki Nakayama, Atsushi Doi