Patents by Inventor Nozomu Akagi

Nozomu Akagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9954073
    Abstract: A method for manufacturing a SiC semiconductor device includes: forming recesses to be separated from each other on a cross section in parallel to a surface of the substrate by partially removing a top portion of the drift layer with etching using a mask after arranging the mask on a front surface of a drift layer; forming electric field relaxation layers having the second conductivity type to be separated from each other on the cross section by ion-implanting a second conductivity type impurity on a bottom of each recess using the mask; and forming a channel layer by forming a second conductivity type layer on the front surface of the drift layer including a front surface of each electric field relaxation layer in a respective recess.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: April 24, 2018
    Assignee: DENSO CORPORATION
    Inventors: Nozomu Akagi, Jun Sakakibara, Shoji Mizuno, Yuichi Takeuchi
  • Publication number: 20170018642
    Abstract: A semiconductor device includes a first conductivity type region provided to at least one of a second conductivity type column region and a second conductivity type layer located on the second conductivity type column region. The first conductivity type region has a non-depletion layer region when a voltage between a first electrode and a second electrode is 0V. When the voltage between the first electrode and the second electrode is a predetermined voltage, a depletion layer formed on interfaces between a first conductivity type column region and the second conductivity type column region as well as the first conductivity type column region and the second conductivity type layer and a depletion layer formed between the first conductivity type region and an interface of a region provided with the first conductivity type region connect to each other.
    Type: Application
    Filed: March 16, 2015
    Publication date: January 19, 2017
    Inventors: Yuma KAGATA, Nozomu AKAGI
  • Publication number: 20170012108
    Abstract: In a method for manufacturing a semiconductor device, when a second conductive type impurity layer is formed to provide a deep layer having a second conductive type in a first concavity and to provide a channel layer having the second conductive type on a surface of a drift layer, an epitaxial growth is performed under a growth condition that a contact trench provided by a recess is formed on a surface of a part of the second conductive type impurity layer corresponding to a center position of the first concavity, and a contact region is formed by ion-implanting a second conductive type impurity on a bottom of the contact trench.
    Type: Application
    Filed: January 14, 2015
    Publication date: January 12, 2017
    Inventors: Jun SAKAKIBARA, Nozomu AKAGI, Shoji MIZUNO, Yuichi TAKEUCHI, Katsumi SUZUKI
  • Publication number: 20170012109
    Abstract: A method for manufacturing a SiC semiconductor device includes: forming recesses to be separated from each other on a cross section in parallel to a surface of the substrate by partially removing a top portion of the drift layer with etching using a mask after arranging the mask on a front surface of a drift layer; forming electric field relaxation layers having the second conductivity type to be separated from each other on the cross section by ion-implanting a second conductivity type impurity on a bottom of each recess using the mask; and forming a channel layer by forming a second conductivity type layer on the front surface of the drift layer including a front surface of each electric field relaxation layer in a respective recess.
    Type: Application
    Filed: January 14, 2015
    Publication date: January 12, 2017
    Inventors: Nozomu AKAGI, Jun SAKAKIBARA, Shoji MIZUNO, Yuichi TAKEUCHI
  • Patent number: 9478621
    Abstract: The element electrodes of a semiconductor element are disposed in a cell region, while an outermost peripheral electrode electrically connected to a semiconductor substrate is disposed in a peripheral region. In the peripheral region, a second-conductivity-type layer is disposed above a super-junction structure. A potential division region is disposed above the second-conductivity-type layer to electrically connect the element electrodes and the outermost peripheral electrode and also divide the voltage between the element electrodes and the outermost peripheral electrode into a plurality of stages. A part of the potential division region overlaps the peripheral region when viewed from the thickness direction of the semiconductor substrate.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: October 25, 2016
    Assignee: DENSO CORPORATION
    Inventors: Nozomu Akagi, Yuma Kagata, Makoto Kuwahara
  • Patent number: 8823083
    Abstract: A semiconductor device includes a vertical semiconductor element having a super junction structure constructed of a first conductivity-type drift layer disposed on a surface of a semiconductor substrate and second conductivity-type regions having a stripe shape defining a longitudinal direction in one direction and being arranged at a predetermined column pitch in the drift layer. When a surplus concentration obtained by dividing a difference between an electrical charge of the second conductivity-type region and an electrical charge of a first conductivity-type region by the column pitch is i, a depth of the super junction structure is z, a surplus concentration gradient as a change of the surplus concentration i per unit depth dz is di/dz, and a central withstand voltage in which a margin is added to a desired withstand voltage is Vmax, the super junction structure is configured such that the surplus concentration gradient di/dz satisfies a relation of 0 > ? i ? z > - ( 7.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: September 2, 2014
    Assignee: DENSO CORPORATION
    Inventors: Yuma Kagata, Nozomu Akagi
  • Patent number: 8815701
    Abstract: A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: August 26, 2014
    Assignee: Denso Corporation
    Inventors: Masakiyo Sumitomo, Makoto Asai, Nozomu Akagi, Yasuhiro Kitamura, Hiroki Nakamura, Tetsuo Fujii
  • Publication number: 20140203356
    Abstract: A semiconductor device including a vertical semiconductor element has a trench gate structure and a dummy gate structure. The trench gate structure includes a first trench that penetrates a first impurity region and a base region to reach a first conductivity-type region in a super junction structure. The dummy gate structure includes a second trench that penetrates the base region reach the super junction structure and is formed to be deeper than the first trench.
    Type: Application
    Filed: August 30, 2012
    Publication date: July 24, 2014
    Applicant: DENSO CORPORATION
    Inventors: Yuma Kagata, Nozomu Akagi
  • Publication number: 20140151785
    Abstract: The element electrodes of a semiconductor element are disposed in a cell region, while an outermost peripheral electrode electrically connected to a semiconductor substrate is disposed in a peripheral region. In the peripheral region, a second-conductivity-type layer is disposed above a super-junction structure. A potential division region is disposed above the second-conductivity-type layer to electrically connect the element electrodes and the outermost peripheral electrode and also divide the voltage between the element electrodes and the outermost peripheral electrode into a plurality of stages. A part of the potential division region overlaps the peripheral region when viewed from the thickness direction of the semiconductor substrate.
    Type: Application
    Filed: September 4, 2012
    Publication date: June 5, 2014
    Applicant: DENSO CORPORATION
    Inventors: Nozomu Akagi, Yuma Kagata, Makoto Kuwahara
  • Patent number: 8519748
    Abstract: A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a conduction state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: August 27, 2013
    Assignee: DENSO CORPORATION
    Inventors: Takaaki Aoki, Shoji Mizuno, Shigeki Takahashi, Takashi Nakano, Nozomu Akagi, Yoshiyuki Hattori, Makoto Kuwahara, Kyoko Okada
  • Patent number: 8446003
    Abstract: A semiconductor device includes a multilayer wiring substrate and a double-sided multi-electrode chip. The double-sided multi-electrode chip includes a semiconductor chip and has multiple electrodes on both sides of the semiconductor chip. The double-sided multi-electrode chip is embedded in the multilayer wiring substrate in such a manner that the double-sided multi-electrode chip is not exposed outside the multilayer wiring substrate. The electrodes of the double-sided multi-electrode chip are connected to wiring layers of the multilayer wiring substrate.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: May 21, 2013
    Assignee: DENSO CORPORATION
    Inventors: Atsushi Komura, Yasuhiro Kitamura, Nozomu Akagi, Yasutomi Asai
  • Patent number: 8436419
    Abstract: A semiconductor device includes a high-breakdown-voltage transistor having a semiconductor layer. The semiconductor layer has an element portion and a wiring portion. The element portion has a first wiring on a front side of the semiconductor layer and a backside electrode on a back side of the semiconductor layer. The element portion is configured as a vertical transistor that causes an electric current to flow in a thickness direction of the semiconductor layer between the first wiring and the backside electrode. The backside electrode is elongated to the wiring portion. The wiring portion has a second wiring on the front side of the semiconductor layer. The wiring portion and the backside electrode provide a pulling wire that allows the electric current to flow to the second wiring.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: May 7, 2013
    Assignee: DENSO CORPORATION
    Inventors: Akira Yamada, Nozomu Akagi
  • Patent number: 8384153
    Abstract: A semiconductor device includes: a substrate; multiple first and second conductive type regions on the substrate for providing a super junction structure; a channel layer on the super junction structure; a first conductive type layer in the channel layer; a contact second conductive type region in the channel layer; a gate electrode on the channel layer via a gate insulation film; a surface electrode on the channel layer; a backside electrode on the substrate opposite to the super junction structure; and an embedded second conductive type region. The embedded second conductive type region is disposed in a corresponding second conductive type region, protrudes into the channel layer, and contacts the contact second conductive type region. The embedded second conductive type region has an impurity concentration higher than the channel layer, and has a maximum impurity concentration at a position in the corresponding second conductive type region.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: February 26, 2013
    Assignee: DENSO CORPORATION
    Inventors: Tsuyoshi Yamamoto, Masakiyo Sumitomo, Hitoshi Yamaguchi, Nozomu Akagi, Yuma Kagata
  • Publication number: 20120302036
    Abstract: A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.
    Type: Application
    Filed: July 11, 2012
    Publication date: November 29, 2012
    Applicant: DENSO CORPORATION
    Inventors: Masakiyo Sumitomo, Makoto Asai, Nozomu Akagi, Yasuhiro Kitamura, Hiroki Nakamura, Tetsuo Fujii
  • Patent number: 8278731
    Abstract: A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: October 2, 2012
    Assignee: DENSO CORPORATION
    Inventors: Masakiyo Sumitomo, Makoto Asai, Nozomu Akagi, Yasuhiro Kitamura, Hiroki Nakamura, Tetsuo Fujii
  • Publication number: 20120182051
    Abstract: A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a conduction state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector.
    Type: Application
    Filed: March 29, 2012
    Publication date: July 19, 2012
    Applicant: DENSO CORPORATION
    Inventors: Takaaki Aoki, Shoji Mizuno, Shigeki Takahashi, Takashi Nakano, Nozomu Akagi, Yoshiyuki Hattori, Makoto Kuwahara, Kyoko Okada
  • Patent number: 8179169
    Abstract: A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a conduction state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: May 15, 2012
    Assignee: Denso Corporation
    Inventors: Takaaki Aoki, Shoji Mizuno, Shigeki Takahashi, Takashi Nakano, Nozomu Akagi, Yoshiyuki Hattori, Makoto Kuwahara, Kyoko Okada
  • Publication number: 20120049271
    Abstract: A semiconductor device includes a high-breakdown-voltage transistor having a semiconductor layer. The semiconductor layer has an element portion and a wiring portion. The element portion has a first wiring on a front side of the semiconductor layer and a backside electrode on a back side of the semiconductor layer. The element portion is configured as a vertical transistor that causes an electric current to flow in a thickness direction of the semiconductor layer between the first wiring and the backside electrode. The backside electrode is elongated to the wiring portion. The wiring portion has a second wiring on the front side of the semiconductor layer. The wiring portion and the backside electrode provide a pulling wire that allows the electric current to flow to the second wiring.
    Type: Application
    Filed: November 8, 2011
    Publication date: March 1, 2012
    Applicant: DENSO CORPORATION
    Inventors: Akira YAMADA, Nozomu Akagi
  • Patent number: 8097921
    Abstract: A semiconductor device includes a high-breakdown-voltage transistor having a semiconductor layer. The semiconductor layer has an element portion and a wiring portion. The element portion has a first wiring on a front side of the semiconductor layer and a backside electrode on a back side of the semiconductor layer. The element portion is configured as a vertical transistor that causes an electric current to flow in a thickness direction of the semiconductor layer between the first wiring and the backside electrode. The backside electrode is elongated to the wiring portion. The wiring portion has a second wiring on the front side of the semiconductor layer. The wiring portion and the backside electrode provide a pulling wire that allows the electric current to flow to the second wiring.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: January 17, 2012
    Assignee: DENSO CORPORATION
    Inventors: Akira Yamada, Nozomu Akagi
  • Publication number: 20120007173
    Abstract: A semiconductor device includes: a substrate; multiple first and second conductive type regions on the substrate for providing a super junction structure; a channel layer on the super junction structure; a first conductive type layer in the channel layer; a contact second conductive type region in the channel layer; a gate electrode on the channel layer via a gate insulation film; a surface electrode on the channel layer; a backside electrode on the substrate opposite to the super junction structure; and an embedded second conductive type region. The embedded second conductive type region is disposed in a corresponding second conductive type region, protrudes into the channel layer, and contacts the contact second conductive type region. The embedded second conductive type region has an impurity concentration higher than the channel layer, and has a maximum impurity concentration at a position in the corresponding second conductive type region.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 12, 2012
    Applicant: DENSO CORPORATION
    Inventors: Tsuyoshi YAMAMOTO, Masakiyo SUMITOMO, Hitoshi YAMAGUCHI, Nozomu AKAGI, Yuma KAGATA