Abstract: A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a flow of software executed by the first logical processor. The RTIT packets are stored in an RTIT queue corresponding to the first logical processor. The RTIT packets are transferred from the RTIT queue to memory predominantly with firmware of the processor. Other methods, apparatus, and systems are also disclosed.

Abstract: A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device. The processing device further includes at least one register communicably coupled to the LBR counter, the at least one register to provide an LBR structure comprising a plurality of LBR entries. An LBR entry of the plurality of LBR entries includes an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter in response to creation of the LBR entry.

Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

Abstract: Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

Abstract: This invention relates to a novel target for production of immune and non-immune based therapeutics and for disease diagnosis. More particularly, the invention provides therapeutic antibodies against KRTCAP3, FAM26F, MGC52498, FAM70A or TMEM154 antigens, which are differentially expressed in cancer, and diagnostic and therapeutic usages. This invention further relates to extracellular domains of KRTCAP3, FAM26F, MGC52498, FAM70A and TMEM154 proteins and variants, and therapeutic usages thereof.

Abstract: A processor includes a front end, a decoder, a retirement unit, and a performance monitoring unit. The front end includes a decoder with logic to receive a tracking instruction to enable tracking of execution of a region of memory. The instruction is to define an address range of the region. The retirement includes logic to retire the tracking instruction and candidate instructions. The performance monitoring unit includes logic to determine that the candidate instructions are associated with an entrance and an exit to the address range, and to generate an alert based on the candidate instructions association with the entrance and the exit.

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.

Abstract: The present invention is directed to PVRIG polypeptides and their uses.

Abstract: Described herein is a method of mitigating, in a subject (individual), tissue injury resulting from exposure to radiation (accidental/unintentional or intentional, such as therapeutic), chemoradiotherapy, disease, toxin, or drug or biologic mediated therapy.

Abstract: Described herein is a method of mitigating, in a subject (individual), tissue injury resulting from exposure to radiation (accidental/unintentional or intentional, such as therapeutic), chemoradiotherapy, disease, toxin, or drug or biologic mediated therapy.

Abstract: Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first event counter counts the occurrences of a type of event within the processor and outputs a signal to activate a second event counter in response to reaching a first predefined count. The second event counter counts the occurrences of the type of event within the processor and causes an interrupt of the processor in response to reaching a second predefined count.

Abstract: This invention relates to a novel target for production of immune and non-immune based therapeutics and for disease diagnosis. More particularly, the invention provides therapeutic antibodies against VSIG1, ILDR1, LOC253012, AI216611, C1ORF32 or FXYD3 antigens, which are predicted co-stimulatory family members and which are differentially expressed in cancers including, lung cancer, ovarian cancer, and colon cancer, and diagnostic and therapeutic usages. The use of these antibodies for modulating B7 costimulation and related therapies such as the treatment of autoimmunity are also provided. This invention further relates to the discovery of extracellular domains of VSIG1 and its variants, FXYD3 and its variants, ILDR1 and its variants, LOC253012 and its variants, AI216611 and its variants, and C1ORF32 and its variants awhich are suitable targets for immunotherapy, cancer therapy, and drug development.

Abstract: Stabilizing apparatus for inclined legs comprises a thigh engageable portion extending generally transversally along the width of the lap of a subject with which the apparatus is bodily engaged, two spaced appendage portions extending downwardly from the thigh engageable portion, a foot engageable portion positionable on an underlying surface, and a portion, such a connecting element and tensioning device, extending from each of the two appendage portions to a foot engageable portion. The two appendage portions are positionable to be substantially in contact with the lateral side of a thigh of the subject. A loop is defined such that each of the portions extending from an appendage portion to a foot engageable portion is suitably tensioned so as to apply forces to a foot engageable portion for resisting a forward foot sliding motion and to an appendage portion for resisting relative transversal motion of an inclined leg.

Abstract: This invention relates to VSTM5 proteins, soluble molecules and fusions thereof which are suitable targets for drug development and for treatment of immune related disorders, immunotherapy, treatment of cancer, infectious disorders and/or sepsis.

Abstract: The present invention relates to VSTM5-specific antibodies, antibody fragments, and VSTM5 polypeptides, conjugates and compositions comprising same, for modulating (antagonizing or agonizing) one or more of the effects of VSTM5 expression on immunity. More specifically, the present invention relates to VSTM5-specific antibodies, antibody fragments, and VSTM5 polypeptides, conjugates and compositions comprising same for treating and aiding in the diagnosis of cancer, infectious diseases and immune related diseases, e.g., those associated with aberrant (higher or lower than normal) VSTM5 expression by diseased and/or immune cells and/or aberrant (increased or reduced) VSTM5-mediated effects on immunity.

Abstract: A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device. The processing device further includes at least one register communicably coupled to the LBR counter, the at least one register to provide an LBR structure comprising a plurality of LBR entries. An LBR entry of the plurality of LBR entries includes an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter in response to creation of the LBR entry.

Abstract: This invention relates to a novel target for production of immune and non-immune based therapeutics and for disease diagnosis. More particularly, the invention provides therapeutic antibodies against VSIG1, ILDR1, LOC253012, AI216611, C1ORF32 or FXYD3 antigens, which are predicted co-stimulatory family members and which are differentially expressed in cancers including, lung cancer, ovarian cancer, and colon cancer, and diagnostic and therapeutic usages. The use of these antibodies for modulating B7 costimulation and related therapies such as the treatment of autoimmunity are also provided. This invention further relates to the discovery of extracellular domains of VSIG1 and its variants, FXYD3 and its variants, ILDR1 and its variants, LOC253012 and its variants, AI216611 and its variants, and C1ORF32 and its variants awhich are suitable targets for immunotherapy, cancer therapy, and drug development.

Abstract: A method comprises filtering branch trap events at a branch event filter, monitoring a branch event filter to capture indirect branch trap events that cause a control flow trap exception, receiving the indirect branch trap events at a handler and the handler processing the indirect branch trap events

Abstract: A processor includes a front end, a decoder, a retirement unit, and a performance monitoring unit. The front end includes a decoder with logic to receive a tracking instruction to enable tracking of execution of a region of memory. The instruction is to define an address range of the region. The retirement includes logic to retire the tracking instruction and candidate instructions. The performance monitoring unit includes logic to determine that the candidate instructions are associated with an entrance and an exit to the address range, and to generate an alert based on the candidate instructions association with the entrance and the exit.

Abstract: A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device and an LBR structure communicably coupled to the LBR counter. The LBR structure comprises a plurality of LBR entries. Furthermore, an LBR entry of the plurality of LBR entries comprises an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter when the LBR entry is created.