Abstract: A stage circuit includes a first driver, a second driver, a first output unit and a second output unit. The first driver controls voltages of first and second nodes, according to a first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a first clock signal supplied to a second input terminal, and a second clock signal supplied to a third input terminal. The second driver controls a voltage of a third node, according to the first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a carry signal of a next stage supplied to a fourth input terminal, and the voltage of the second node.

Abstract: A data driver and a display device including the same. The data driver includes a DA converting circuit converting a digital signal into an analog signal and an output circuit disposed downstream of the DA converting circuit. The output circuit outputs two selected color data signals and one black voltage based on the data state of one reference data signal, and outputs one fixed color data signal.

Abstract: A Successive Approximation Register (SAR) analog-to-digital converting apparatus includes a reference voltage supply unit suitable for supplying different reference voltages depending on bits of a pixel output signal to be converted, an N bit SAR analog-to-digital conversion unit suitable for sequentially converting upper N?1 bits and lower N bits of the pixel output signal by selectively using the reference voltages supplied from the reference voltage supply unit, where N is a natural number, and an error correction unit suitable for calculating an error correction value based on a difference between conversion results of the lower N bits, and outputting a 2N?2 bit analog-to-digital conversion result by combining converted upper N?1 bits and converted lower N bits and correcting an error of the reference voltages using the error correction value in the combining.

Abstract: A display device includes a plurality of display pixels, a plurality of data lines that are connected to the display pixels, and a plurality of sensing lines that are connected to the display pixels. Each display pixel includes a driving transistor comprising a first terminal, a second terminal, and a third terminal, a capacitor connected to the first terminal of the driving transistor, a first switching transistor connected to the data line and the first terminal of the driving transistor, a light-emitting element connected to the third terminal of the driving transistor configured to emit light, a second switching transistor connected between the sensing line and the light-emitting element, and a third switching transistor connected between the third terminal of the driving transistor and the light-emitting element.

Abstract: An apparatus for driving a two-dimensional transducer array, a medical imaging system and a method of driving a two-dimensional transducer array are provided. An apparatus for driving a two-dimensional (2D) transducer array including one or more transducers includes one or more drivers configured to respectively drive the transducers, each of the drivers including a register, a comparator, a pulse frequency setter, a multi-pulse controller, a transmission signal generator, a signal transceiver, a transmission and reception switch, and a reception signal amplifier, and a driving controller configured to control the drivers.

Abstract: Disclosed herein are a high voltage switching circuit which includes one or more main switching devices connected to one or more current sources, and a control circuit unit configured to control a potential difference between terminals of each of the main switching devices within a predetermined range by receiving current from the one or more current sources.

Abstract: A first reference voltage is applied to a plurality of pixels during a data writing period when data is written and a second reference voltage is applied to the plurality of pixels during a light emitting period when the plurality of pixels emit light, in which each of the plurality of pixels includes a switching transistor to transfer a data voltage applied to a data line to a first node; a driving transistor controlling a driving current flowing into an OLED according to the voltage of the first node and a first power supply voltage; and a storage capacitor including a first electrode connected to the first node and a second electrode receiving one of the first reference voltage and the second reference voltage. A difference between the first reference voltage and the second reference voltage is determined according to a threshold voltage deviation characteristic of the display unit.

Abstract: Arithmetic memories, image sensors including the arithmetic memories and methods of operating the arithmetic memories are provided. The arithmetic memories may include an input block to which a digital pixel reset signal and a digital pixel image signal are input and a plurality of unit cells configured to generate a digital difference signal. The input block may include first and second multiplexers to which the digital pixel reset signal and the digital pixel image signal are input and an inverter connected to the first multiplexer. The plurality of unit cells may include a first unit cell connected to the input block and a second unit cell through an N-th unit cell successively connected to the first unit cell. N may be two or greater. The first unit cell may include third and fourth multiplexers, a first flip/flop, and a first AND gate.

Abstract: An analog-digital converting device includes a successive approximation register (SAR) analog-digital converting circuit suitable for resolving upper N-bits for an input signal, a single-slope (SS) analog-digital converting circuit suitable for resolving lower M-bits for the input signal after the SAR analog-digital converting circuit resolves the upper N-bits, and a combining circuit suitable for combining the upper N-bits and the lower M-bits.

Abstract: An analog-to-digital converter includes a digital-to-analog converter comprising a capacitor divider network comprising a plurality of dividing capacitors and a dummy capacitor. The digital-to-analog converter is configured to selectively apply an input voltage and a reference voltage to the dividing capacitors and to selectively apply the input voltage and a shift voltage to the dummy capacitor. The analog-to-digital converter further includes a comparison circuit configured to compare an output of the capacitor divider network and a common mode voltage and a shift voltage generator circuit configured to generate the shift voltage. The shift voltage generator circuit may be configured to vary the shift voltage for different samples of the input voltage. For example, the shift voltage generator circuit may be configured to change the shift voltage for succeeding samples by an amount corresponding to 1/(2?M) times the reference voltage to support 2?M oversampling of the input voltage.

Abstract: A display device and a method of driving the same are provided. The display device includes a plurality of display pixels, a plurality of data lines that are connected to the display pixels, and a plurality of sensing lines that are connected to the display pixels. Each display pixel includes: a driving transistor that has a control terminal, an input terminal, and an output terminal; a capacitor that is connected to the control terminal of the driving transistor; a first switching transistor that is connected to the data line and the control terminal of the driving transistor; a light-emitting element that receives a driving current from the driving transistor to emit light; a second switching transistor that is connected between the sensing line and the light-emitting element; and a third switching transistor that is connected between the output terminal of the driving transistor and the light-emitting element.

Abstract: A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase.

Abstract: A method of driving an organic light emitting display capable of providing a sufficient (e.g., a sufficiently long) data writing period and/or threshold voltage compensating period is provided. The method includes supplying scan signals to odd scan lines in a writing period of an odd frame set to be in a non-emission state, and supplying scan signals to even scan lines in a writing period of an even frame set to be in the non-emission state.

Abstract: A Successive Approximation Register (SAR) analog-to-digital converting apparatus includes a reference voltage supply unit suitable for supplying different reference voltages depending on bits of a pixel output signal to be converted, an N bit SAR analog-to-digital conversion unit suitable for sequentially converting upper N?1 bits and lower N bits of the pixel output signal by selectively using the reference voltages supplied from the reference voltage supply unit, where N is a natural number, and an error correction unit suitable for calculating an error correction value based on a difference between conversion results of the lower N bits, and outputting a 2N?2 bit analog-to-digital conversion result by combining converted upper N?1 bits and converted lower N bits and correcting an error of the reference voltages using the error correction value in the combining.

Abstract: A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.

Abstract: Disclosed are a touch panel driving apparatus and a display device including the same, which lead to the enhancement of sensing sensitivity. The touch panel driving apparatus includes a touch control unit and a touch sensing unit. The touch sensing unit is connected to the receiving lines, and generates the digital touch information on the basis of change of a capacitance between two transmitting lines and one receiving line or generates the digital touch information on the basis of change of a capacitance of each of the receiving lines to supply the digital touch information to the touch control unit, according to the sensing control signal.

Abstract: A gate driver, including multiple stages of gate driving circuits, wherein each stage of the gate driving circuits includes an input part configured to generate a Q node signal in response to a carry signal of one of previous stages and a clock signal, the Q node signal being applied to Q node, an output part configured to output a gate output signal to a gate output terminal in response to the Q node signal, and a charge sharing part connected to the gate output terminal of a present stage and a gate output terminal of one of next stages, the charge sharing part configured to operate charge-sharing between the gate output signal of the present stage and a gate output signal of one of the next stages in response to a select signal.

Abstract: A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit and a second output unit. The first driver controls voltages of first and second nodes, according to a first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a first clock signal supplied to a second input terminal, and a second clock signal supplied to a third input terminal. The second driver controls a voltage of a third node, according to the first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a carry signal of a next stage supplied to a fourth input terminal, and the voltage of the second node.