Patents by Inventor Olin L. Hartin
Olin L. Hartin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9048110Abstract: An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.Type: GrantFiled: March 13, 2013Date of Patent: June 2, 2015Assignee: FREESCALE SEMICONDUCTOR INC.Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin
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Patent number: 8957496Abstract: An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit. The metal ring has a first gap and the ring-shaped region has a second gap.Type: GrantFiled: April 17, 2013Date of Patent: February 17, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Qiang Li, Olin L. Hartin, Sateh Jalaleddine, Radu M. Secareanu, Michael J. Zunino
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Publication number: 20140312457Abstract: An electronic apparatus includes a semiconductor substrate, a circuit block disposed in and supported by the semiconductor substrate and comprising an inductor, and a discontinuous noise isolation guard ring surrounding the circuit block. The discontinuous noise isolation guard ring includes a metal ring supported by the semiconductor substrate and a ring-shaped region disposed in the semiconductor substrate, having a dopant concentration level, and electrically coupled to the metal ring, to inhibit noise in the semiconductor substrate from reaching the circuit. The metal ring has a first gap and the ring-shaped region has a second gap.Type: ApplicationFiled: April 17, 2013Publication date: October 23, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Qiang Li, Olin L. Hartin, Sateh Jalaleddine, Radu M. Secareanu, Michael J. Zunino
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Patent number: 8761699Abstract: Embodiments of antennas and radio frequency (RF) modules include a substrate, a first antenna arm coupled to the substrate, and a first conductive structure between a distal end of the first antenna arm and a bottom surface of the substrate. An embodiment of a system includes a first substrate, a first conductive structure on a top surface of the first substrate, and an antenna coupled to the top surface of the first substrate. The antenna includes a second substrate, a first antenna arm coupled to the second substrate, and a second conductive structure having a proximal end and a distal end. The proximal end of the second conductive structure is coupled to a distal end of the first antenna arm, and the distal end of the second conductive structure extends to a bottom surface of the second substrate and is coupled to the first conductive structure on the first substrate.Type: GrantFiled: December 28, 2011Date of Patent: June 24, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Qiang Li, Jon T. Adams, Olin L. Hartin
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Patent number: 8725095Abstract: An embodiment of an antenna includes a radiation frame and a planar inverted-F antenna (PIFA). The radiation frame has a frame shape that defines a central opening. The PIFA includes an antenna arm, a feed arm, and a shorting arm. A distal end of the shorting arm is conductively coupled with the radiation frame. The antenna may be coupled to a substrate of an RF module. The RF module may be included in a system that also includes a non-RF component that produces a signal for transmission. In such a system, the RF module is configured to receive the signal, convert the signal to an RF signal, and radiate the RF signal over an air interface.Type: GrantFiled: December 28, 2011Date of Patent: May 13, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Qiang Li, Jon T. Adams, Olin L. Hartin
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Publication number: 20130207229Abstract: An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.Type: ApplicationFiled: March 13, 2013Publication date: August 15, 2013Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin
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Publication number: 20130171951Abstract: Embodiments of antennas and radio frequency (RF) modules include a substrate, a first antenna arm coupled to the substrate, and a first conductive structure between a distal end of the first antenna arm and a bottom surface of the substrate. An embodiment of a system includes a first substrate, a first conductive structure on a top surface of the first substrate, and an antenna coupled to the top surface of the first substrate. The antenna includes a second substrate, a first antenna arm coupled to the second substrate, and a second conductive structure having a proximal end and a distal end. The proximal end of the second conductive structure is coupled to a distal end of the first antenna arm, and the distal end of the second conductive structure extends to a bottom surface of the second substrate and is coupled to the first conductive structure on the first substrate.Type: ApplicationFiled: December 28, 2011Publication date: July 4, 2013Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Qiang Li, Jon T. Adams, Olin L. Hartin
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Publication number: 20130171950Abstract: An embodiment of an antenna includes a radiation frame and a planar inverted-F antenna (PIFA). The radiation frame has a frame shape that defines a central opening. The PIFA includes an antenna arm, a feed arm, and a shorting arm. A distal end of the shorting arm is conductively coupled with the radiation frame. The antenna may be coupled to a substrate of an RF module. The RF module may be included in a system that also includes a non-RF component that produces a signal for transmission. In such a system, the RF module is configured to receive the signal, convert the signal to an RF signal, and radiate the RF signal over an air interface.Type: ApplicationFiled: December 28, 2011Publication date: July 4, 2013Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Qiang Li, Jon T. Adams, Olin L. Hartin
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Patent number: 7961063Abstract: A balanced-unbalanced (balun) signal transformer includes an unbalanced port, a balanced port coupled to the unbalanced port, the balanced port comprising a first terminal and a second terminal, a first capacitor coupled to the first terminal, a first inductor coupled to ground and the first capacitor, a second capacitor coupled to the second terminal, and a second inductor coupled to ground and the second capacitor. The transformer may also include a third capacitor coupled to a terminal of the unbalanced port; and a third inductor coupled to the third capacitor and the third terminal.Type: GrantFiled: July 31, 2008Date of Patent: June 14, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Lianjun Liu, Jonathan K. Abrokwah, Olin L. Hartin, Qiang Li
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Patent number: 7834428Abstract: Apparatus and a method are provided for reducing noise in mixed-signal and digital circuits. One apparatus (200) includes a metal-oxide-semiconductor field-effect transistor (MOSFET) (210). MOSFET (210) includes a doped substrate (2210) with a source formed proximate a substrate tie (2224) and a substrate tie (2250) adjacent substrate (2210). A ground rail (255) is coupled to the source and substrate tie (2224), and a ground rail (285) is coupled to substrate tie (2250). Ground rails (255) and (285) are configured to be coupled to different ground networks (250 and 280). One method includes producing a model of a semiconductor device including a standard semiconductor cell (710). The semiconductor cell is identified as a noise-sensitive or a noise-producing semiconductor cell (720), and the semiconductor cell is replaced with a corresponding noise-aware semiconductor cell (730).Type: GrantFiled: February 28, 2007Date of Patent: November 16, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Radu M. Secareanu, Olin L. Hartin, Emre Salman
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Patent number: 7741718Abstract: Apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect (40, 42, 44) configured to couple to a first region of the substrate, a first gate (22, 24, 26, 28) coupled to the first interconnect and configured to receive a first differential input, a second interconnect (30, 32, 34, 36, 38) parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate (20) coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.Type: GrantFiled: November 23, 2009Date of Patent: June 22, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Suman K. Banerjee, Alain C. Duvalley, Olin L. Hartin, Craig Jasper, Walter Parmon
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Patent number: 7683483Abstract: Flip-chip electronic devices (40, 70, 80, 90) employ bumps (42, 72, 82) for coupling to an external substrate. Device cells (43, 73, 83, 93) and bumps (42, 72, 82) are preferably arranged in clusters (46) where four bumps (42, 72, 82) substantially surround each device cell (43, 73, 83, 93) or form a cross with the device cell (43, 73, 83, 93) at the intersection of the cross. The bumps (42, 72, 82) are desirably spaced apart by the minimum allowable bump (42, 72, 82) pitch (Lm). Typically, each device cell (43, 73, 83, 93) contains one or more active device regions (44, 74, 86, 96) depending on the overall function. Complex devices (40, 70) are formed by an X-Y array of the clusters (46), where adjacent clusters (46) may share bumps (43, 73, 83, 93) and/or device cells (43, 73, 83, 93). In a preferred embodiment, the bumps (42, 82) form the outer perimeter (48) of the device (40, 80, 90). The maximum device temperature and overall noise is reduced.Type: GrantFiled: February 5, 2007Date of Patent: March 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin, Sandra J. Wipf
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Patent number: 7683486Abstract: Method and apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect (40, 42, 44) configured to couple to a first region of the substrate, a first gate (22, 24, 26, 28) coupled to the first interconnect and configured to receive a first differential input, a second interconnect (30, 32, 34, 36, 38) parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate (20) coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.Type: GrantFiled: December 9, 2005Date of Patent: March 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Suman K. Banerjee, Alain C. Duvallet, Craig Jasper, Olin L. Hartin, Walter Parmon
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Patent number: 7683733Abstract: An electronic assembly includes a substrate (66), a balun transformer (42) formed on the substrate (66) and including a first winding (50) and a second winding (52), each having respective first and second ends, and a reaction circuit component (48) formed on the substrate (66) and electrically coupled to the second winding (52) between the first and second ends thereof. The balun transformer (42) and the reaction circuit component (48) jointly form a harmonically suppressed balun transformer having a fundamental frequency, and the reaction circuit component (48) is tuned such that the harmonically suppressed balun transformer resonates at a selected harmonic of the fundamental frequency.Type: GrantFiled: February 4, 2008Date of Patent: March 23, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Qiang Li, Jonathan K. Abrokwah, Olin L. Hartin, Lianjun Liu
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Publication number: 20100065968Abstract: Apparatus are provided for routing interconnects of a dual-gate electronic device operating in a differential configuration. An electronic apparatus formed on a substrate is provided comprising a first interconnect (40, 42, 44) configured to couple to a first region of the substrate, a first gate (22, 24, 26, 28) coupled to the first interconnect and configured to receive a first differential input, a second interconnect (30, 32, 34, 36, 38) parallel to the first interconnect and configured to couple to a second region of the substrate, and a second gate (20) coupled to the second interconnect and configured to receive a second differential input. The first gate is parallel to the first interconnect, and the second gate is parallel to the second interconnect.Type: ApplicationFiled: November 23, 2009Publication date: March 18, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Suman K. Banerjee, Alain C. Duvallet, Olin L. Hartin, Craig Jasper, Walter Parmon
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Publication number: 20100059860Abstract: An improved varactor diode (40) is obtained by providing a substrate (41) having a first surface (43), in which are formed a P+ region (53, 46) proximate the first surface (43), a first N region (54, 45) located beneath the P+ region (53, 46), an N well region (56, 44) located beneath the first N region (54, 45) and a first P counter-doped region (55) located between the first N region (54, 45) and the N well region (56, 44), thereby forming an P+NPN structure for the varactor diode. In some embodiments, a second P-type counter-doped region (59) is provided within the N-well region (56, 44) so as to reduce the N doping concentration within the N well region (56, 44) but without creating a further PN junction therein. The net doping profile (52) provides varactor diodes (40) having a larger tuning ratio than varactors (20) without such counter-doped regions. By interchanging N and P regions an N+PNP varactor is obtained.Type: ApplicationFiled: September 9, 2008Publication date: March 11, 2010Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Chun-Li Liu, Olin L. Hartin, Jay P. John, James A. Kirchgessner, Vishal P. Trivedi
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Publication number: 20100026411Abstract: A balanced-unbalanced (balun) signal transformer includes an unbalanced port, a balanced port coupled to the unbalanced port, the balanced port comprising a first terminal and a second terminal, a first capacitor coupled to the first terminal, a first inductor coupled to ground and the first capacitor, a second capacitor coupled to the second terminal, and a second inductor coupled to ground and the second capacitor. The transformer may also include a third capacitor coupled to a terminal of the unbalanced port; and a third inductor coupled to the third capacitor and the third terminal.Type: ApplicationFiled: July 31, 2008Publication date: February 4, 2010Inventors: LIANJUN LIU, Jonathan K. Abrokwah, Olin L. Hartin, Qiang Li
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Publication number: 20090302440Abstract: An integrated circuit includes a p-well block region having a low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region and a grounded, highly doped region for providing additional noise isolation.Type: ApplicationFiled: July 30, 2009Publication date: December 10, 2009Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin
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Patent number: 7608913Abstract: An integrated circuit includes a p-well block region having a high resistivity due to low doping concentration formed in a region of a substrate for providing noise isolation between a first circuit block and a second circuit block. The integrated circuit further includes a guard region formed surrounding the p-well block region for providing noise isolation between the first circuit block and the second circuit block.Type: GrantFiled: February 23, 2006Date of Patent: October 27, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Radu M. Secareanu, Suman K. Banerjee, Olin L. Hartin
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Patent number: 7595679Abstract: A system-on-chip or other circuit has an on-chip noise-free ground which is added to divert ground noise from the sensitive nodes. An on-chip decoupling capacitor, tuned in resonance with the parasitic inductance of the interconnects, can be provided to add an additional low impedance ground path.Type: GrantFiled: April 12, 2006Date of Patent: September 29, 2009Assignee: University of RochesterInventors: Mikhail Popovich, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin