Patents by Inventor Oliver Haeberlen

Oliver Haeberlen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11114554
    Abstract: A high-electron-mobility semiconductor device includes: a buffer region having first, second and third cross-sections forming a stepped lateral profile, the first cross-section being thicker than the third cross-section and comprising a first buried field plate disposed therein, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections; and a barrier region of substantially uniform thickness extending along the stepped lateral profile of the buffer region, the barrier region being separated from the first buried field plate by a portion of the buffer region. The buffer region is formed by a first semiconductor material and the barrier region is formed by a second semiconductor material.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: September 7, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Häberlen
  • Publication number: 20210234028
    Abstract: A transistor device includes a gate fin that is a segment of a semiconductor body disposed between a pair of gate trenches formed in an upper surface of the semiconductor body, a plurality of two-dimensional charge carrier gas channels disposed at different vertical depths within the gate fin, source and drain contacts arranged on either side of the gate fin in a current flow direction of the gate fin, the source and drain contacts each being electrically connected to each one of the two-dimensional charge carrier gas channels, and a gate structure that is configured to control a conductive connection between the source and drain contacts. The gate structure includes a region of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and a conductive gate electrode formed over the region of doped type III-nitride semiconductor material.
    Type: Application
    Filed: January 28, 2020
    Publication date: July 29, 2021
    Inventors: Thomas Detzel, Gerhard Prechtl, Oliver Haeberlen
  • Patent number: 11069782
    Abstract: A semiconductor device includes a transistor in a semiconductor body having a main surface. The transistor includes a source region; a drain region; a body region; a drift zone; a gate electrode at the body region, the body region and the drift zone being disposed along a first direction between the source region and the drain region, and the first direction being parallel to the main surface; a field plate disposed in each of a plurality of field plate trenches, each of the field plate trenches having a longitudinal axis extending along the first direction; and a field dielectric layer between the field plate and the drift zone, a thickness of the field dielectric layer at a bottom of each of the field plate trenches gradually increases along the first direction, the thickness being measured along a depth direction of the plurality of field plate trenches.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: July 20, 2021
    Inventors: Andreas Meiser, Oliver Haeberlen
  • Patent number: 11004966
    Abstract: A semiconductor device is described. In one embodiment, the device includes a Group-III nitride channel layer and a Group-III nitride barrier layer on the Group-III nitride channel layer, wherein the Group-III nitride barrier layer includes a first portion and a second portion, the first portion having a thickness less than the second portion. A p-doped Group-III nitride gate layer section is arranged at least on the first portion of the Group-III nitride barrier layer and a gate contact formed on the p-doped Group-III nitride gate layer.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: May 11, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Walter Rieger
  • Publication number: 20210134968
    Abstract: In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.
    Type: Application
    Filed: October 26, 2020
    Publication date: May 6, 2021
    Inventors: Oliver Haeberlen, Eric G. Persson, Reenu Garg
  • Publication number: 20210050439
    Abstract: An enhancement mode Group III nitride-based transistor device includes a body having a first surface and a Group III nitride barrier layer arranged on a Group III nitride channel layer and forming a heterojunction therebetween. A first cell field includes transistor cells and an edge region. Each transistor cell includes source, gate and drain fingers extending substantially parallel to one another on the first surface in a longitudinal direction. The gate finger, arranged laterally between the source and drain fingers, includes a p-doped Group III nitride finger arranged between a metallic gate finger and the first surface. The edge region surrounds the transistor cells and includes an edge termination structure having an isolation ring and a p-doped Group III nitride runner. The isolation ring locally interrupts the heterojunction. The runner, extending transversely to the longitudinal direction, is located laterally between the isolation ring and an end of the drain finger.
    Type: Application
    Filed: August 10, 2020
    Publication date: February 18, 2021
    Inventors: Gerhard Prechtl, Gilberto Curatola, Oliver Haeberlen
  • Patent number: 10840353
    Abstract: A semiconductor device includes a heterojunction semiconductor body including a first and second type III-V semiconductor layers with different bandgaps such that a first two-dimensional charge carrier gas forms at an interface between the two layers. The second type III-V semiconductor layer includes a thicker section and a thinner section. A first input-output electrode is on the thicker section and is in ohmic contact with the first two-dimensional charge carrier gas. A second input-output electrode is formed on the thinner section and is in ohmic contact with the first two-dimensional charge carrier gas. A gate structure is formed on the thinner section and is configured to control a conductive connection between the first and second input-output electrodes. The gate structure is laterally spaced apart from a transition between the thicker and thinner sections of the second type III-V semiconductor layer.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: November 17, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Oliver Haeberlen
  • Publication number: 20200321447
    Abstract: In an embodiment, a Group III nitride-based transistor device, includes a first. Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction. capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first. Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length ld, and 0 nm?ld?200 nm.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 8, 2020
    Inventors: Clemens Ostermaier, Oliver Haeberlen, Gerhard Prechtl, Manuel Stabentheiner
  • Patent number: 10763246
    Abstract: A device includes a driver circuit, a first semiconductor chip monolithically integrated with the driver circuit in a first semiconductor material, and a second semiconductor chip integrated in a second semiconductor material. The second semiconductor material is a compound semiconductor.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: September 1, 2020
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Klaus Schiess, Oliver Haeberlen, Matteo-Alessandro Kutschak
  • Patent number: 10680069
    Abstract: In accordance with an embodiment, a circuit includes a first gallium nitride (GaN) transistor comprising a drain coupled to a drain node, a source coupled to a source node, and a gate coupled to a gate node; and a second GaN transistor comprising a drain coupled to the drain node, a source coupled to a first power source node configured to be coupled to a first capacitor.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: June 9, 2020
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Oliver Haeberlen, Gerald Deboy
  • Publication number: 20200119162
    Abstract: A semiconductor device includes a heterojunction semiconductor body including a first and second type III-V semiconductor layers with different bandgaps such that a first two-dimensional charge carrier gas forms at an interface between the two layers. The second type III-V semiconductor layer includes a thicker section and a thinner section. A first input-output electrode is on the thicker section and is in ohmic contact with the first two-dimensional charge carrier gas. A second input-output electrode is formed on the thinner section and is in ohmic contact with the first two-dimensional charge carrier gas. A gate structure is formed on the thinner section and is configured to control a conductive connection between the first and second input-output electrodes. The gate structure is laterally spaced apart from a transition between the thicker and thinner sections of the second type III-V semiconductor layer.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Gilberto Curatola, Oliver Haeberlen
  • Patent number: 10600710
    Abstract: A semiconductor device includes a group III-semiconductor-nitride-based channel layer, a group III-semiconductor-nitride-based barrier layer formed on the channel layer, a two-dimensional electron gas channel formed in the channel layer, a first current electrode and a second current electrode formed on the barrier layer and laterally spaced from each other, and a gate structure formed on the barrier layer between the first and second current electrodes. The barrier layer has a symmetrically shaped recess between the first and second current electrodes, the symmetrically shaped recess including a first recess portion formed in a part of an upper surface of the barrier layer and a second recess portion formed within the first recess portion. The gate structure includes a group III-semiconductor-nitride-based doped layer that fills the symmetrically shaped recess and an electrically conductive gate electrode formed on an upper side of the doped layer that is opposite from the barrier layer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: March 24, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Häberlen
  • Publication number: 20200044036
    Abstract: A semiconductor device includes a transistor in a semiconductor body having a main surface. The transistor includes a source region; a drain region; a body region; a drift zone; a gate electrode at the body region, the body region and the drift zone being disposed along a first direction between the source region and the drain region, and the first direction being parallel to the main surface; a field plate disposed in each of a plurality of field plate trenches, each of the field plate trenches having a longitudinal axis extending along the first direction; and a field dielectric layer between the field plate and the drift zone, a thickness of the field dielectric layer at a bottom of each of the field plate trenches gradually increases along the first direction, the thickness being measured along a depth direction of the plurality of field plate trenches.
    Type: Application
    Filed: October 15, 2019
    Publication date: February 6, 2020
    Applicant: Infineon Technologies AG
    Inventors: Andreas MEISER, Oliver HAEBERLEN
  • Publication number: 20200044032
    Abstract: In accordance with an embodiment, a circuit includes a first gallium nitride (GaN) transistor comprising a drain coupled to a drain node, a source coupled to a source node, and a gate coupled to a gate node; and a second GaN transistor comprising a drain coupled to the drain node, a source coupled to a first power source node configured to be coupled to a first capacitor.
    Type: Application
    Filed: August 3, 2018
    Publication date: February 6, 2020
    Inventors: Oliver Haeberlen, Gerald Deboy
  • Patent number: 10541313
    Abstract: A method of forming a semiconductor device includes providing a heterojunction semiconductor body. The heterojunction semiconductor body includes a first type III-V semiconductor layer and a second type III-V semiconductor layer formed over the first type III-V semiconductor layer. The second type III-V semiconductor layer has a different bandgap as the first type III-V semiconductor layer such that a first two-dimensional charge carrier gas forms at an interface between the first and second type III-V semiconductor layers. The second type III-V semiconductor layer has a thicker section and a thinner section. A first input-output electrode is formed on the thicker section. A gate structure and a second input-output are formed on the thinner section. The gate structure is laterally spaced apart from a transition between the thicker and thinner sections of the second type III-V semiconductor layer.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: January 21, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Oliver Haeberlen
  • Patent number: 10516023
    Abstract: A method of forming a semiconductor device includes providing a heterojunction semiconductor body. The heterojunction semiconductor body includes a type III-V semiconductor back-barrier region, a type III-V semiconductor channel layer formed on the back-barrier region, and a type III-V semiconductor barrier layer formed on the back-barrier region. A first two-dimensional charge carrier gas is at an interface between the channel and barrier layers. A second two-dimensional charge carrier gas is disposed below the first two-dimensional charge carrier gas. A deep contact structure in the heterojunction semiconductor body that extends through the channel layer and forms an interface with the second two-dimensional charge carrier gas is formed. The first semiconductor region includes a first contact material that provides a conductive path for majority carriers of the second two-dimensional charge carrier gas at the interface with the second two-dimensional charge carrier gas.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: December 24, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Oliver Haeberlen
  • Patent number: 10483360
    Abstract: A method of manufacturing a semiconductor device is providing, which includes forming a trench in a semiconductor substrate, forming an oxide layer over sidewalls and over a bottom side of the trench, performing an ion implantation process, forming a cover layer, and patterning the covering layer, thereby forming an uncovered area and a covered area of the oxide layer, respectively. The method further includes performing an isotropic etching process thereby removing portions of the uncovered area of the oxide layer and removing a part of a surface portion of the covered area adjacent to the uncovered portions, and removing remaining portions of the covering layer.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: November 19, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Oliver Haeberlen
  • Patent number: 10431504
    Abstract: A semiconductor disk of a first crystalline material, which has a first lattice system, is bonded on a process surface of a base substrate, wherein a bonding layer is formed between the semiconductor disk and the base substrate. A second semiconductor layer of a second crystalline material with a second, different lattice system is formed by epitaxy on a first semiconductor layer formed from the semiconductor disk.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: October 1, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Wolfgang Lehnert, Rudolf Berger, Albert Birner, Helmut Brech, Oliver Häberlen, Guenther Ruhl, Roland Rupp
  • Patent number: 10418319
    Abstract: A method of manufacturing a semiconductor device includes providing an electrically conductive carrier and placing a semiconductor chip over the carrier. The method includes applying an electrically insulating layer over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. The method includes selectively removing the electrically insulating layer and applying solder material where the electrically insulating layer is removed and on the second face of the electrically insulating layer.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: September 17, 2019
    Assignee: Infineon Technologies AG
    Inventors: Oliver Haeberlen, Klaus Schiess, Stefan Kramp
  • Publication number: 20190280093
    Abstract: A method of forming a semiconductor device includes providing a heterojunction semiconductor body. The heterojunction semiconductor body includes a type III-V semiconductor back-barrier region, a type III-V semiconductor channel layer formed on the back-barrier region, and a type III-V semiconductor barrier layer formed on the back-barrier region. A first two-dimensional charge carrier gas is at an interface between the channel and barrier layers. A second two-dimensional charge carrier gas is disposed below the first two-dimensional charge carrier gas. A deep contact structure in the heterojunction semiconductor body that extends through the channel layer and forms an interface with the second two-dimensional charge carrier gas is formed. The first semiconductor region includes a first contact material that provides a conductive path for majority carriers of the second two-dimensional charge carrier gas at the interface with the second two-dimensional charge carrier gas.
    Type: Application
    Filed: March 6, 2018
    Publication date: September 12, 2019
    Inventors: Gilberto Curatola, Oliver Haeberlen