Patents by Inventor Oliver Haeberlen

Oliver Haeberlen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10763246
    Abstract: A device includes a driver circuit, a first semiconductor chip monolithically integrated with the driver circuit in a first semiconductor material, and a second semiconductor chip integrated in a second semiconductor material. The second semiconductor material is a compound semiconductor.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: September 1, 2020
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Klaus Schiess, Oliver Haeberlen, Matteo-Alessandro Kutschak
  • Patent number: 10680069
    Abstract: In accordance with an embodiment, a circuit includes a first gallium nitride (GaN) transistor comprising a drain coupled to a drain node, a source coupled to a source node, and a gate coupled to a gate node; and a second GaN transistor comprising a drain coupled to the drain node, a source coupled to a first power source node configured to be coupled to a first capacitor.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: June 9, 2020
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Oliver Haeberlen, Gerald Deboy
  • Publication number: 20200119162
    Abstract: A semiconductor device includes a heterojunction semiconductor body including a first and second type III-V semiconductor layers with different bandgaps such that a first two-dimensional charge carrier gas forms at an interface between the two layers. The second type III-V semiconductor layer includes a thicker section and a thinner section. A first input-output electrode is on the thicker section and is in ohmic contact with the first two-dimensional charge carrier gas. A second input-output electrode is formed on the thinner section and is in ohmic contact with the first two-dimensional charge carrier gas. A gate structure is formed on the thinner section and is configured to control a conductive connection between the first and second input-output electrodes. The gate structure is laterally spaced apart from a transition between the thicker and thinner sections of the second type III-V semiconductor layer.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Gilberto Curatola, Oliver Haeberlen
  • Patent number: 10600710
    Abstract: A semiconductor device includes a group III-semiconductor-nitride-based channel layer, a group III-semiconductor-nitride-based barrier layer formed on the channel layer, a two-dimensional electron gas channel formed in the channel layer, a first current electrode and a second current electrode formed on the barrier layer and laterally spaced from each other, and a gate structure formed on the barrier layer between the first and second current electrodes. The barrier layer has a symmetrically shaped recess between the first and second current electrodes, the symmetrically shaped recess including a first recess portion formed in a part of an upper surface of the barrier layer and a second recess portion formed within the first recess portion. The gate structure includes a group III-semiconductor-nitride-based doped layer that fills the symmetrically shaped recess and an electrically conductive gate electrode formed on an upper side of the doped layer that is opposite from the barrier layer.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: March 24, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Häberlen
  • Publication number: 20200044036
    Abstract: A semiconductor device includes a transistor in a semiconductor body having a main surface. The transistor includes a source region; a drain region; a body region; a drift zone; a gate electrode at the body region, the body region and the drift zone being disposed along a first direction between the source region and the drain region, and the first direction being parallel to the main surface; a field plate disposed in each of a plurality of field plate trenches, each of the field plate trenches having a longitudinal axis extending along the first direction; and a field dielectric layer between the field plate and the drift zone, a thickness of the field dielectric layer at a bottom of each of the field plate trenches gradually increases along the first direction, the thickness being measured along a depth direction of the plurality of field plate trenches.
    Type: Application
    Filed: October 15, 2019
    Publication date: February 6, 2020
    Applicant: Infineon Technologies AG
    Inventors: Andreas MEISER, Oliver HAEBERLEN
  • Publication number: 20200044032
    Abstract: In accordance with an embodiment, a circuit includes a first gallium nitride (GaN) transistor comprising a drain coupled to a drain node, a source coupled to a source node, and a gate coupled to a gate node; and a second GaN transistor comprising a drain coupled to the drain node, a source coupled to a first power source node configured to be coupled to a first capacitor.
    Type: Application
    Filed: August 3, 2018
    Publication date: February 6, 2020
    Inventors: Oliver Haeberlen, Gerald Deboy
  • Patent number: 10541313
    Abstract: A method of forming a semiconductor device includes providing a heterojunction semiconductor body. The heterojunction semiconductor body includes a first type III-V semiconductor layer and a second type III-V semiconductor layer formed over the first type III-V semiconductor layer. The second type III-V semiconductor layer has a different bandgap as the first type III-V semiconductor layer such that a first two-dimensional charge carrier gas forms at an interface between the first and second type III-V semiconductor layers. The second type III-V semiconductor layer has a thicker section and a thinner section. A first input-output electrode is formed on the thicker section. A gate structure and a second input-output are formed on the thinner section. The gate structure is laterally spaced apart from a transition between the thicker and thinner sections of the second type III-V semiconductor layer.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: January 21, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Oliver Haeberlen
  • Patent number: 10516023
    Abstract: A method of forming a semiconductor device includes providing a heterojunction semiconductor body. The heterojunction semiconductor body includes a type III-V semiconductor back-barrier region, a type III-V semiconductor channel layer formed on the back-barrier region, and a type III-V semiconductor barrier layer formed on the back-barrier region. A first two-dimensional charge carrier gas is at an interface between the channel and barrier layers. A second two-dimensional charge carrier gas is disposed below the first two-dimensional charge carrier gas. A deep contact structure in the heterojunction semiconductor body that extends through the channel layer and forms an interface with the second two-dimensional charge carrier gas is formed. The first semiconductor region includes a first contact material that provides a conductive path for majority carriers of the second two-dimensional charge carrier gas at the interface with the second two-dimensional charge carrier gas.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: December 24, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Gilberto Curatola, Oliver Haeberlen
  • Patent number: 10483360
    Abstract: A method of manufacturing a semiconductor device is providing, which includes forming a trench in a semiconductor substrate, forming an oxide layer over sidewalls and over a bottom side of the trench, performing an ion implantation process, forming a cover layer, and patterning the covering layer, thereby forming an uncovered area and a covered area of the oxide layer, respectively. The method further includes performing an isotropic etching process thereby removing portions of the uncovered area of the oxide layer and removing a part of a surface portion of the covered area adjacent to the uncovered portions, and removing remaining portions of the covering layer.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: November 19, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Oliver Haeberlen
  • Patent number: 10431504
    Abstract: A semiconductor disk of a first crystalline material, which has a first lattice system, is bonded on a process surface of a base substrate, wherein a bonding layer is formed between the semiconductor disk and the base substrate. A second semiconductor layer of a second crystalline material with a second, different lattice system is formed by epitaxy on a first semiconductor layer formed from the semiconductor disk.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: October 1, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Wolfgang Lehnert, Rudolf Berger, Albert Birner, Helmut Brech, Oliver Häberlen, Guenther Ruhl, Roland Rupp
  • Patent number: 10418319
    Abstract: A method of manufacturing a semiconductor device includes providing an electrically conductive carrier and placing a semiconductor chip over the carrier. The method includes applying an electrically insulating layer over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. The method includes selectively removing the electrically insulating layer and applying solder material where the electrically insulating layer is removed and on the second face of the electrically insulating layer.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: September 17, 2019
    Assignee: Infineon Technologies AG
    Inventors: Oliver Haeberlen, Klaus Schiess, Stefan Kramp
  • Publication number: 20190280093
    Abstract: A method of forming a semiconductor device includes providing a heterojunction semiconductor body. The heterojunction semiconductor body includes a type III-V semiconductor back-barrier region, a type III-V semiconductor channel layer formed on the back-barrier region, and a type III-V semiconductor barrier layer formed on the back-barrier region. A first two-dimensional charge carrier gas is at an interface between the channel and barrier layers. A second two-dimensional charge carrier gas is disposed below the first two-dimensional charge carrier gas. A deep contact structure in the heterojunction semiconductor body that extends through the channel layer and forms an interface with the second two-dimensional charge carrier gas is formed. The first semiconductor region includes a first contact material that provides a conductive path for majority carriers of the second two-dimensional charge carrier gas at the interface with the second two-dimensional charge carrier gas.
    Type: Application
    Filed: March 6, 2018
    Publication date: September 12, 2019
    Inventors: Gilberto Curatola, Oliver Haeberlen
  • Publication number: 20190280100
    Abstract: A method of forming a semiconductor device includes providing a heterojunction semiconductor body. The heterojunction semiconductor body includes a first type III-V semiconductor layer and a second type III-V semiconductor layer formed over the first type III-V semiconductor layer. The second type III-V semiconductor layer has a different bandgap as the first type III-V semiconductor layer such that a first two-dimensional charge carrier gas forms at an interface between the first and second type III-V semiconductor layers. The second type III-V semiconductor layer has a thicker section and a thinner section. A first input-output electrode is formed on the thicker section. A gate structure and a second input-output are formed on the thinner section. The gate structure is laterally spaced apart from a transition between the thicker and thinner sections of the second type III-V semiconductor layer.
    Type: Application
    Filed: March 6, 2018
    Publication date: September 12, 2019
    Inventors: Gilberto Curatola, Oliver Haeberlen
  • Patent number: 10388736
    Abstract: In an embodiment, a method includes forming an intentionally doped superlattice laminate on a support substrate, forming a Group III nitride-based device having a heterojunction on the superlattice laminate layer, and forming a charge blocking layer between the heterojunction and the superlattice laminate.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: August 20, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Horst Schäfer, Oliver Häberlen
  • Patent number: 10304923
    Abstract: A method of manufacturing a semiconductor die includes forming a semiconductor body on a substrate. The semiconductor body has a periphery which is devoid of active devices and terminates at an edge face of the semiconductor die. The semiconductor body includes a first III-nitride semiconductor layer and a plurality of second III-nitride semiconductor layers below the first III-nitride semiconductor layer. The method further includes forming an uninsulated connection structure which extends vertically in the periphery of the semiconductor body and provides a vertical leakage path for at least some of the second III-nitride semiconductor layers either to the substrate or to a metallization layer disposed above the semiconductor body, but not to both. Additional semiconductor die manufacturing methods are provided.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: May 28, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Clemens Ostermaier, Gerhard Prechtl, Oliver Häberlen
  • Patent number: 10290566
    Abstract: In an embodiment, an electronic component includes a high-voltage depletion mode transistor including a current path coupled in series with a current path of a low-voltage enhancement mode transistor, a diode including an anode and a cathode, and a die pad. A rear surface of the high-voltage depletion mode transistor is mounted on and electrically coupled to the die pad. A first current electrode of the low-voltage enhancement mode transistor is mounted on and electrically coupled to the die pad. The anode of the diode is coupled to a control electrode of the high-voltage depletion mode transistor, and the cathode of the diode is mounted on the die pad.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: May 14, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess, Oliver Haeberlen, Matteo-Alessandro Kutschak
  • Patent number: 10283634
    Abstract: A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: May 7, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Joachim Krumrey, Franz Hirler, Walter Rieger
  • Publication number: 20190096779
    Abstract: A semiconductor device includes a group III-semiconductor-nitride-based channel layer, a group III-semiconductor-nitride-based barrier layer formed on the channel layer, a two-dimensional electron gas channel formed in the channel layer, a first current electrode and a second current electrode formed on the barrier layer and laterally spaced from each other, and a gate structure formed on the barrier layer between the first and second current electrodes. The barrier layer has a symmetrically shaped recess between the first and second current electrodes, the symmetrically shaped recess including a first recess portion formed in a part of an upper surface of the barrier layer and a second recess portion formed within the first recess portion. The gate structure includes a group III-semiconductor-nitride-based doped layer that fills the symmetrically shaped recess and an electrically conductive gate electrode formed on an upper side of the doped layer that is opposite from the barrier layer.
    Type: Application
    Filed: November 30, 2018
    Publication date: March 28, 2019
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Häberlen
  • Patent number: 10199216
    Abstract: In an embodiment, a method includes treating an edge region of a wafer including a substrate having an upper surface and one or more epitaxial Group III nitride layers arranged on the upper surface of the substrate, so as to remove material including at least one Group III element from the edge region.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: February 5, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Clemens Ostermaier, Gerhard Prechtl, Oliver Haeberlen
  • Patent number: 10177061
    Abstract: In an embodiment, a semiconductor device includes a substrate, a Group III nitride-based semiconductor layer formed on the substrate, a first current electrode and a second current electrode formed on the Group III nitride-based semiconductor layer and spaced from each other, and a control electrode formed on the Group III nitride-based semiconductor layer between the first current electrode and the second current electrode. The control electrode includes at least a middle portion, configured to switch off a channel below the middle portion when a first voltage is applied to the control electrode, and second portions adjoining the middle portion. The second portions are configured to switch off a channel below the second portions when a second voltage is applied to the control electrode, the second voltage being less than the first voltage and the second voltage being less than a threshold voltage of the second portions.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: January 8, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Clemens Ostermaier, Oliver Haeberlen