Patents by Inventor Oliver Kiehl

Oliver Kiehl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8704541
    Abstract: A circuit testing interface and test method are disclosed. The circuit testing interface may include a test current transmitting pad, a test voltage measuring pad, and at least one driving circuit comprising an output terminal. The output terminal of the at least one driving circuit may be coupled to a through-silicon via (TSV). The circuit testing interface may further include at least one switch module, coupled to (1) the output terminal of the driving circuit, (2) the test current transmitting pad, and (3) the test voltage measuring pad.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: April 22, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Bret Dale, Oliver Kiehl
  • Patent number: 8704529
    Abstract: A circuit test interface and a test method are disclosed. The circuit test interface may include a test voltage input pad, a test voltage output pad, and a plurality of input buffers. Each of the plurality of input buffers may have a first input terminal, a second input terminal, and an output terminal. The first input terminal of each respective input buffer may be coupled to one of a plurality of through-silicon vias (TSVs). The circuit test interface may further include a plurality of switch units. Each of the plurality of switch units may have a first terminal and a second terminal. The circuit test interface may further include a scan chain, coupled to both the output terminal of each of the plurality of input buffers and to the test voltage output pad.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: April 22, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Bret Dale, Oliver Kiehl
  • Publication number: 20130141124
    Abstract: A circuit testing interface and test method are disclosed. The circuit testing interface may include a test current transmitting pad, a test voltage measuring pad, and at least one driving circuit comprising an output terminal. The output terminal of the at least one driving circuit may be coupled to a through-silicon via (TSV). The circuit testing interface may further include at least one switch module, coupled to (1) the output terminal of the driving circuit, (2) the test current transmitting pad, and (3) the test voltage measuring pad.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 6, 2013
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Bret Dale, Oliver Kiehl
  • Publication number: 20130082718
    Abstract: A circuit test interface and a test method are disclosed. The circuit test interface may include a test voltage input pad, a test voltage output pad, and a plurality of input buffers. Each of the plurality of input buffers may have a first input terminal, a second input terminal, and an output terminal. The first input terminal of each respective input buffer may be coupled to one of a plurality of through-silicon vias (TSVs). The circuit test interface may further include a plurality of switch units. Each of the plurality of switch units may have a first terminal and a second terminal. The circuit test interface may further include a scan chain, coupled to both the output terminal of each of the plurality of input buffers and to the test voltage output pad.
    Type: Application
    Filed: October 4, 2011
    Publication date: April 4, 2013
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Bret Dale, Oliver Kiehl
  • Patent number: 8368422
    Abstract: A testing circuit for verifying the impedance of off-chip drivers includes: a plurality of off-chip drivers (OCD), each off-chip driver including a through-silicon via (TSV); an IREF test pad, for driving a current to the plurality of off-chip drivers; a plurality of pre-drivers, each respective pre-driver coupled to one of the plurality of off-chip drivers, wherein the plurality of pre-drivers are configured to turn on the off-chip drivers; a VREF test pad, for inputting a reference voltage to the testing circuit; a plurality of input buffers (IB) for outputting a plurality of comparison results, each of the plurality of input buffers configured to output the plurality of comparison results according to the reference voltage and the voltage at the TSV nodes; and a test pad, coupled to the plurality of IBs, for receiving the comparison results to determine whether the impedance of each OCD is within a desired range.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: February 5, 2013
    Assignee: Nanya Technology Corp.
    Inventors: Bret Roberts Dale, Oliver Kiehl
  • Patent number: 8138610
    Abstract: A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: March 20, 2012
    Assignee: Qimonda AG
    Inventors: Jong Hoon Oh, Klaus Hummler, Oliver Kiehl, Josef Schnell, Wayne Frederick Ellis, Jung Pil Kim, Lee Ward Collins, Octavian Beldiman
  • Patent number: 7975170
    Abstract: A refresh scheduler is configured to refresh memory cells of a memory device according to a plurality of refresh intervals. The various refresh intervals are determined in response to refresh errors.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: July 5, 2011
    Assignee: Qimonda AG
    Inventors: Klaus Hummler, Jong Hoon Oh, Wayne Frederick Ellis, Jung Pill Kim, Oliver Kiehl, Josef Schnell, Octavian Beldiman, Lee Ward Collins
  • Patent number: 7944047
    Abstract: Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: May 17, 2011
    Assignee: Qimonda AG
    Inventors: Jong Hoon Oh, Klaus Hummler, Oliver Kiehl, Josef Schnell, Wayne Frederick Ellis, Jung Pill Kim, Lee Ward Collins, Octavian Beldiman
  • Patent number: 7882324
    Abstract: Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: February 1, 2011
    Assignee: Qimonda AG
    Inventors: Josef Schnell, Klaus Hummler, Jong Hoon Oh, Wayne Frederick Ellis, Jung Pill Kim, Oliver Kiehl, Octavian Beldiman, Lee Ward Collins
  • Patent number: 7721010
    Abstract: Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory device, while command decoding logic of the second memory device is bypassed.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 18, 2010
    Assignee: Qimonda North America Corp.
    Inventors: Josef Schnell, Klaus Hummler, Jong Hoon Oh, Wayne Frederick Ellis, Jung Pill Kim, Oliver Kiehl, Octavian Beldiman, Lee Ward Collins
  • Patent number: 7694196
    Abstract: The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least one non-volatile memory chip, and at least one fail signature register for storing fail signature data related to memory errors detected in the MCP. The controller can poll the fail signature register for fail signature data related to memory errors stored therein. Upon detection of fail signature data, the controller can store the fail signature data on a fail signature register located on a non-volatile memory.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: April 6, 2010
    Assignee: Qimonda North America Corp.
    Inventors: Josef Schnell, Klaus Hummler, Jong Hoon Oh, Wayne Frederick Ellis, Jung Pill Kim, Oliver Kiehl, Octavian Beldiman, Lee Ward Collins
  • Patent number: 7688665
    Abstract: Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: March 30, 2010
    Assignee: Qimonda North America Corp.
    Inventors: Jung Pill Kim, Jong Hoon Oh, Oliver Kiehl, Josef Schnell, Klaus Hummler, Wayne Frederick Ellis, Octavian Beldiman, Lee Ward Collins
  • Patent number: 7636250
    Abstract: A random access memory including a first amplifier, a second amplifier, a first data path, a second data path, and a first circuit. The first data path receives first data via first memory cells and the second data path receives second data via second memory cells. The first circuit is configured to receive the first data via the first data path and the second data via the second data path. The first circuit is configured to selectively provide the first data to the first amplifier and the second amplifier and the second data to the first amplifier and the second amplifier.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: December 22, 2009
    Assignee: Qimonda North America Corp.
    Inventors: Jiyoon Chung, Oliver Kiehl
  • Publication number: 20090200652
    Abstract: A multi-chip package is provided that has at least a first, second and third chip, each comprising a top and bottom surface. The multi-chip package also has a package substrate for interfacing with a printed circuit board (PCB). The chips and the package substrate are housed within an encapsulation material. The bottom surface of the first chip is attached to the package substrate. The top surface of the first chip has a first plurality of landing pads, which serve as a mechanical and electrical interface between the first and second chip. The bottom surface of the second chip has a second plurality of landing pads that serve as a mechanical and electrical interface between the second and first chip. Additionally, the top surface of the second chip has a third plurality of landing pads that serve as a mechanical and electrical interface between the second and third chip.
    Type: Application
    Filed: February 8, 2008
    Publication date: August 13, 2009
    Inventors: Jong Hoon Oh, Klaus Hummler, Oliver Kiehl, Josef Schnell, Wayne Frederick Ellis, Jung Pil Kim, Lee Ward Collins, Octavian Beldiman
  • Patent number: 7539034
    Abstract: A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory.
    Type: Grant
    Filed: February 1, 2007
    Date of Patent: May 26, 2009
    Assignee: Qimonda North America Corp.
    Inventors: Jung Pill Kim, Jong-Hoon Oh, Oliver Kiehl, Josef Schnell, Klaus Hummler, Wayne Ellis, Octavian Beldiman, Lee Collins
  • Publication number: 20090129186
    Abstract: The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least one non-volatile memory chip, and at least one fail signature register for storing fail signature data related to memory errors detected in the MCP. The controller can poll the fail signature register for fail signature data related to memory errors stored therein. Upon detection of fail signature data, the controller can store the fail signature data on a fail signature register located on a non-volatile memory.
    Type: Application
    Filed: November 20, 2007
    Publication date: May 21, 2009
    Inventors: Josef Schnell, Klaus Hummler, Jong Hoon Oh, Wayne Frederick Ellis, Jung Pill Kim, Oliver Kiehl, Octavian Beldiman, Lee Ward Collins
  • Publication number: 20090113158
    Abstract: Embodiments of the invention generally provide a system, method and memory device for accessing memory. One embodiment includes synchronization circuitry configured to determine timing skew between a first memory device and a second memory device, and introduce a delta delay to at least one of the first memory device and the second memory device to adjust the timing skew.
    Type: Application
    Filed: October 30, 2007
    Publication date: April 30, 2009
    Inventors: Josef Schnell, Klaus Hummler, Jong Hoon Oh, Wayne Frederick Ellis, Jung Pill Kim, Oliver Kiehl, Octavian Beldiman, Lee Ward Collins
  • Publication number: 20090113078
    Abstract: Embodiments of the invention generally provide a system, method, and memory device for accessing memory. In one embodiment, a first memory device includes command decoding logic configured to decode commands issued to the first memory device and a second memory device, while command decoding logic of the second memory device is bypassed.
    Type: Application
    Filed: October 31, 2007
    Publication date: April 30, 2009
    Inventors: JOSEF SCHNELL, Klaus Hummler, Jong Hoon Oh, Wayne Frederick Ellis, Jung Pill Kim, Oliver Kiehl, Octavian Beldiman, Lee Ward Collins
  • Publication number: 20090079055
    Abstract: Embodiments of the present invention generally provide techniques and apparatus for altering the functionality of a multi-chip package (MCP) without requiring entire replacement of the MCP. The MCP may be designed with a top package substrate designed to interface with an add-on package that, when sensed by the MCP, alters the functionality of the MCP.
    Type: Application
    Filed: September 25, 2007
    Publication date: March 26, 2009
    Inventors: JONG HOON OH, Klaus Hummler, Oliver Kiehl, Josef Schnell, Wayne Frederick Ellis, Jung Pill Kim, Lee Ward Collins, Octavian Beldiman
  • Publication number: 20090080279
    Abstract: Embodiments of the invention generally provide an apparatus and technique for sharing an internally generated voltage between devices of a multi-chip package (MCP). The internally generated voltage may be shared via a conductive structure that electrically couples the devices and carries the internally generated voltage.
    Type: Application
    Filed: September 25, 2007
    Publication date: March 26, 2009
    Inventors: JUNG PILL KIM, Jong Hoon Oh, Oliver Kiehl, Josef Schnell, Klaus Hummler, Wayne Frederick Ellis, Octavian Beldiman, Lee Ward Collins