Abstract: A memory device includes a pair of complementary bitlines including a first bitline and a second bitline. A bitline precharge block is coupled between the first bitline and the second bitline. A sense amplifier is coupled to both the first bitline and the second bitline and a sense amplifier precharge block is coupled to the sense amplifier. The sense amplifier precharge block can be activated independently from the bitline precharge block. An isolation block is coupled between the pair of complementary bitlines and the bitline precharge block on one side and the sense amplifier and sense amplifier precharge block on another side.

Abstract: A buffer amplifier architecture for buffering signals which are supplied in parallel to identical chips, particularly DRAM chips, on a semiconductor memory module, is disclosed. The architecture has adjustable delay circuits in each signal line and a delay detector circuit which receives a clock signal from the buffer amplifier architecture at the input and at the output of the buffer amplifier architecture, and takes the phase difference between the two signals to produce a control signal for setting the variable delay time of the delay circuits.

Abstract: System and method for reducing power consumption and noise in a transmission system with an asymmetrically terminated transmission line. A preferred embodiment comprises encoding data words to reduce the number of times a given state appears in a code word. The preferred embodiment comprises counting the number of times a given state appears in a data word. If the count is greater than half of the total number of bits in the data word, then the data word is inverted and a weight bit can be set to the given state. If the count is less than (or equal to) half of the total number of bits, then the data word may be unchanged and the weight bit can be set to the inverse of the given state. The code word can be generated by appending the weight bit to the data word.

Abstract: System and method for detecting a reference signal. A preferred embodiment comprises a latch (such as the latch 320) and a filter (such as the filter 325). The latch tracks a reference signal at its input and reflects the reference signal at its output. The filter can be coupled to the output of the latch and may inject a delay to help eliminate the effects of glitches and noise. When the reference signal reaches a specified value, a control signal from the filter causes the latch to store the reference signal. A delay imparted by the filter ensures that the latch does not store the reference signal until a finite amount of time after the reference signal reaches the specified value.

Abstract: An integrated circuit, comprising: at least one main circuit operable to perform one or more functions, and including at least one I/O node for receiving or transmitting an operating signal; an active termination circuit having first and second MOSFETs of the same type coupled in series across a Vdd node of a first source potential and a Vss node of a second source potential, the at least one I/O node being coupled to a common node between the first and second MOSFETs; and a control circuit operable to bias the first and second MOSFETs such that they exhibit a controlled impedance at the common node.

Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer.

Abstract: A constant current source extending the common-mode range comprises a differential pair of transistors connected to a third current source driving transistor. In an embodiment of the invention, the drains of the differential pair are coupled so as to obtain a common-mode voltage. The gate of the third transistor is connected to the drains of the differential pair in order to regulate current flowing through the third transistor. As the voltage decreases at the drain of the third transistor, the gate voltage on the third transistor increases to compensate for the lost voltage on the drain, thereby keeping the current constant even as the third transistor exits the saturation region.

Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer.

Abstract: A buffer amplifier architecture for buffering signals which are supplied in parallel to identical chips, particularly DRAM chips, on a semiconductor memory module, is disclosed. The architecture has adjustable delay circuits in each signal line and a delay detector circuit which receives a clock signal from the buffer amplifier architecture at the input and at the output of the buffer amplifier architecture, and takes the phase difference between the two signals to produce a control signal for setting the variable delay time of the delay circuits.

Abstract: The present invention provides an apparatus for connecting semiconductor modules, in particular memory banks, having: at least two devices (A, B) for receiving a respective semiconductor module (1, 2); a contact device (13a, 13b, 13c, 13d, 13e, 13f) having a first group of contacts (13a, 13b, 13c, 13d) and a second group of contacts (13e, 13f), the two groups being able to be connected to one another by means of a variable connection module (3, 4); a group of lines (10, 11, 20, 21) for connecting the receiving devices (A, B) to the first group of contacts (13a, 13b, 13c, 13d), a subgroup (13b, 13c) of the first group of contacts being assigned to the lines (10, 11) of the first receiving device (A); the connection module (3, 4) connecting either a subgroup of the contacts (13b, 13c) to the second group of contacts (13e, 13f), or the first group of contacts (13a, 13b, 13c, 13d) to the second group of contacts (13e, 13f).

Abstract: A semiconductor module having a configurable data width of an output bus has data connecting pads as well as driver circuits having a respective output that is connected to an associated data connecting pad. At least one of the data connecting pads, which is not used for interchanging data or commands during operation, is permanently connected to a connection for an internal supply voltage. Thus, in a module configuration with a reduced number of data lines being used, the remaining data lines can be operated at an increased frequency, since the signal-to-ground ratio is improved.

Abstract: The invention relates to an electronic assembly having a non-volatile memory device with a controllable write protection feature and a switching configuration for generating a write protection signal from potentials at the supply terminals of the electronic assembly.

Abstract: A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer.

Abstract: The present invention provides an apparatus for connecting semiconductor modules, in particular memory banks, having: at least two devices (A, B) for receiving a respective semiconductor module (1, 2); a contact device (13a, 13b, 13c, 13d, 13e, 13f) having a first group of contacts (13a, 13b, 13c, 13d) and a second group of contacts (13e, 13f), the two groups being able to be connected to one another by means of a variable connection module (3, 4); a group of lines (10, 11, 20, 21) for connecting the receiving devices (A, B) to the first group of contacts (13a, 13b, 13c, 13d), a subgroup (13b, 13c) of the first group of contacts being assigned to the lines (10, 11) of the first receiving device (A); the connection module (3, 4) connecting either a subgroup of the contacts (13b, 13c) to the second group of contacts (13e, 13f), or the first group of contacts (13a, 13b, 13c, 13d) to the second group of contacts (13e, 13f).

Abstract: A semiconductor module having a configurable data width of an output bus has data connecting pads as well as driver circuits having a respective output that is connected to an associated data connecting pad. At least one of the data connecting pads, which is not used for interchanging data or commands during operation, is permanently connected to a connection for an internal supply voltage. Thus, in a module configuration with a reduced number of data lines being used, the remaining data lines can be operated at an increased frequency, since the signal-to-ground ratio is improved.

Abstract: The invention relates to an electronic assembly having a non-volatile memory device with a controllable write protection feature and a switching configuration for generating a write protection signal from potentials at the supply terminals of the electronic assembly.

Abstract: An integrated circuit has connecting pads for outputting digital signals, a connection for a time reference signal, and an assessment circuit to measure and assess a phase shift between one of the digital signals and the time reference signal. A receiver circuit is connected to a respective junction between one of the connecting pads and an associated output driver. A device for matching propagation times of signals applied to the receiver circuit is provided. The assessment circuit is connected to the receiver circuit and has an output to output a measured result. In each case, the phase shift of the signals to be output in relation to the time reference signal is measured and assessed separately. An offset of the switching edges of the signals to be output can be determined relatively accurately and corrected.

Abstract: An N-bit word is produced from an M-bit code received on an M-bit line, M being larger than N, the M-bit code comprising at least an M-bit code word and a previous M-bit code word, the M-bit code word comprising different levels at at least two bit positions, and the previous M-bit code word comprising levels opposite to the different levels at the corresponding bit positions, by comparing the levels at the two bit positions of the M-bit code word o obtain a first value, comparing the levels at the two corresponding bit positions of the previous M-bit code word to obtain a second value, detecting that the first value is opposite to the second value, and decoding the M-bit code word responsive to detecting that the first value is opposite to the second value. An advantage of the present invention is that all the lines taking part in the transmission have the same electrical characteristics, the same meaning and the same kind of loads.

Abstract: A receiver circuit provides a first stage having an input for receiving input signals and an output node. The first stage includes an amplifier. A second stage has an input coupled to the output of the first stage. The second stage includes a switching circuit coupled to the output node of the first stage for driving the input signals by favoring a rising edge or a falling edge in accordance with a control signal. The second stage also includes a feedback loop coupled to an output of the second stage. The feedback loop provides the control signal for switching the switching circuit to favor the rising edge or falling edge.

Abstract: A receiver circuit includes a first circuit having two modes of operation controlled by a feedback loop. The feedback loop is connected to an output of the first circuit, and the modes of operation include a first mode having a quicker response to an input falling signal edge than a second mode and a second mode with a quicker response to an input rising signal edge than the first mode. A driver stage is integrated into the first circuit to favor the rising edge or the falling edge in accordance with a control signal provided by the feedback loop.