Patents by Inventor Olivier Ferrand

Olivier Ferrand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10983937
    Abstract: In accordance with an embodiment, a method for managing access to a bus shared by interfaces includes: when to the bus is granted to one of the interfaces, triggering a counting having a minimum counting period; and when at least one access request to the bus emanating from at least one other of the interfaces is received during the minimum counting period, releasing the access granted to the one of the interfaces, and creating an arbitration point at an end of the minimum counting period.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: April 20, 2021
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, STMICROELECTRONICS SA
    Inventors: Olivier Ferrand, Daniel Olson, Anis Ben Said, Emmanuel Ardichvili
  • Publication number: 20200302570
    Abstract: An image processing electronic device includes a pipeline configured to process frames of image data; an internal memory coupled to the pipeline, wherein a set of descriptors arranged according to an order is stored in the internal memory, each descriptor of the set of descriptors is associated with a corresponding function to be activated by the pipeline on at least one frame of image data; a controller configured to read each descriptor of the set of descriptors sequentially and cyclically according to the order at a rate of at least one descriptor per one frame of image data and store information corresponding to each read descriptor, wherein the pipeline is configured to activate on each frame of image data, the function associated with each read descriptor based on the stored information.
    Type: Application
    Filed: March 5, 2020
    Publication date: September 24, 2020
    Inventors: Christophe Pinatel, Serge Mazer, Olivier Ferrand
  • Publication number: 20200293474
    Abstract: In accordance with an embodiment, a method for managing access to a bus shared by interfaces includes: when to the bus is granted to one of the interfaces, triggering a counting having a minimum counting period; and when at least one access request to the bus emanating from at least one other of the interfaces is received during the minimum counting period, releasing the access granted to the one of the interfaces, and creating an arbitration point at an end of the minimum counting period.
    Type: Application
    Filed: February 26, 2020
    Publication date: September 17, 2020
    Inventors: Olivier Ferrand, Daniel Olson, Anis Ben Said, Emmanuel Ardichvili
  • Publication number: 20200143738
    Abstract: A method can be used monitoring a task for an electronic module. The method includes waiting for performance of the task, timing the wait, the timing being regulated by a clock signal and generating an alert signal when the timing of the wait has exceeded a reference value. The device can be part of a multimedia interface (e.g., a display) electronic module and the task a graphical task (e.g., an image refresh).
    Type: Application
    Filed: October 31, 2019
    Publication date: May 7, 2020
    Inventor: Olivier Ferrand
  • Publication number: 20200145558
    Abstract: A system includes an electronic module and an integrated circuit outside the electronic module. The integrated circuit is configured to generate a digital timing signal that emulates a first synchronization signal internal to the module and not available outside the module and to generate trigger signals based on the digital timing signal. A controller is configured to independently and autonomously perform control operations of the electronic module at times triggered by the trigger signals.
    Type: Application
    Filed: October 31, 2019
    Publication date: May 7, 2020
    Inventor: Olivier Ferrand
  • Publication number: 20190284422
    Abstract: The present invention relates to an electronic device comprising a printed substrate comprising a trace of molecular ink thereon, the molecular ink being sintered to form a conductive metal trace forming the electronic device, wherein the molecular ink is chosen from a) a flake-less printable composition of 30-60 wt % of a C8-C12 silver carboxylate, 0.1-10 wt % of a polymeric binder and balance of at least one organic solvent, all weights based on total weight of the composition; or b) a flake-less printable composition of 5-75 wt % of bis(2-ethyl-1-hexylamine) copper (II) formate, bis(octylamine) copper (II) formate or tris(octylamine) copper (II) formate, 0.25-10 wt % of a polymeric binder and balance of at least one organic solvent, all weights based on total weight of the composition.
    Type: Application
    Filed: October 25, 2017
    Publication date: September 19, 2019
    Applicants: GGI INTERNATIONAL, NATIONAL RESEARCH COUNCIL OF CANADA, HER MAJESTY THE QUEEN IN RIGHT OF CANADA (...)
    Inventors: Xiangyang LIU, Olga MOZENSON, Bhavana DEORE, Chantal PAQUET, Arnold KELL, Patrick MALENFANT, Julie FERRIGNO, Olivier FERRAND, Jian Xiong HU, Sylvie LAFRENIERE, Reza CHAHARMIR, Jonathan ETHIER, Khelifa HETTAK, Jafar SHAKER, Adrian MOMCIU
  • Patent number: 10402353
    Abstract: An embodiment system includes a first processor configured to process a suite of instructions and a second processor configured to process a subset of the suite of instructions. The system further includes a power management circuit configured to select the first processor or the second processor as a selected processor, the power management circuit being further configured to activate the selected processor or place the selected processor on standby. The system also includes a first peripheral device configured to generate a first interrupt signal, a switch configured to direct the first interrupt signal to the selected processor, and a first memory configured to store a first interrupt routine associated with the first interrupt signal, the selected processor being configured to execute the first interrupt routine in response to the first interrupt signal.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: September 3, 2019
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Dragos Davidescu, Sandrine Lendre, Olivier Ferrand
  • Publication number: 20190251042
    Abstract: A memory access control system includes a first circuit supporting direct access to the memory and a second circuit that is associated with the first circuit and programmed to restrict an area of the memory that is accessible to the first circuit. A central processing unit operates in privileged mode to program the second circuit with a range of addresses within the memory where read and write operations are permitted and further operates in limited mode to program the first circuit with a starting address for read and write operations associated with the task to be executed. Starting execution of the task is performed if the starting address is within the range of addresses. The execution of the task is terminated if an address generated during execution falls outside the range of addresses.
    Type: Application
    Filed: February 13, 2019
    Publication date: August 15, 2019
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Dragos DAVIDESCU, Olivier FERRAND
  • Publication number: 20180189205
    Abstract: An embodiment system includes a first processor configured to process a suite of instructions and a second processor configured to process a subset of the suite of instructions. The system further includes a power management circuit configured to select the first processor or the second processor as a selected processor, the power management circuit being further configured to activate the selected processor or place the selected processor on standby. The system also includes a first peripheral device configured to generate a first interrupt signal, a switch configured to direct the first interrupt signal to the selected processor, and a first memory configured to store a first interrupt routine associated with the first interrupt signal, the selected processor being configured to execute the first interrupt routine in response to the first interrupt signal.
    Type: Application
    Filed: September 11, 2017
    Publication date: July 5, 2018
    Inventors: Dragos Davidescu, Sandrine Lendre, Olivier Ferrand
  • Publication number: 20090165939
    Abstract: A method for manufacturing a complex including a support layer, based on a textile, a foam or a heavy mass, combined with a surface layer based on a polymeric material having a predefined surface state. The method of consisting of: (i) depositing a coating film of the said polymeric material of the surface layer on a sheet of paper having a surface state complementary to the predefined surface state of the complex to be obtained; (ii) calendering the support layer with an intermediate layer based on a second polymeric material obtained by extrusion upstream of the calender, and the assembly formed from the sheet of paper and the coating film; and (iii) withdrawing the sheet of paper.
    Type: Application
    Filed: April 5, 2007
    Publication date: July 2, 2009
    Applicant: Textitles ET Plastiques Chomarat
    Inventors: Olivier Ferrand, Philippe Sanial
  • Patent number: 7421595
    Abstract: A microprocessor includes a computation unit having logic units for executing operations associated with determined instructions of a microprocessor instruction set and a control unit for interpreting the instructions and for controlling the logic units accordingly. An internal timer of the microprocessor is activated by the control unit in response to the execution of a dedicated standby instruction of the microprocessor instruction set. Responsive thereto, a timeout signal is delivered to the control unit so as to place the microprocessor in a standby state during a determined timeout period.
    Type: Grant
    Filed: March 17, 2005
    Date of Patent: September 2, 2008
    Assignee: STMicroelectronics S.A.
    Inventors: Olivier Ferrand, Jean-Michel Gril-Maffre
  • Publication number: 20050216704
    Abstract: A microprocessor has a set of determined instructions which are coded on a determined number P of bits in an instruction coding space of size 2{circumflex over (?)}P. The microprocessor includes a mode register having a determined number N of mode bits. A further included decoding unit and an execution unit are arranged so as to decode and execute a given instruction (Ii) according to at least one first or one second mode of execution as a function of the values of a determined number Qi of mode bits associated with the instruction. The instruction corresponds to distinct respective operations in the first mode of execution and in the second mode of execution where Qi is a strictly positive integer.
    Type: Application
    Filed: March 17, 2005
    Publication date: September 29, 2005
    Applicant: STMicroelectronics S.A.
    Inventors: Olivier Ferrand, Jean-Michel Gril-Maffre
  • Publication number: 20050216779
    Abstract: A microprocessor includes a computation unit for executing operations respectively associated with instructions of a determined set of instructions of the microprocessor. A control unit interprets the instructions and controls the computation unit accordingly. The microprocessor further includes a blocking unit which is controlled by the control unit in response to the execution of a standby instruction belonging to the set of instructions for placing the microprocessor in a standby state during an undetermined period. The exit of the microprocessor from the standby state is conditioned by a determined value or a determined change of the value of a condition bit stored in a condition register, which is internal or external to the microprocessor.
    Type: Application
    Filed: March 16, 2005
    Publication date: September 29, 2005
    Applicant: STMicroelectronics S.A.
    Inventors: Olivier Ferrand, Jean-Michel Gril-Maffre
  • Publication number: 20050216778
    Abstract: A microprocessor includes a computation unit having logic units for executing operations associated with determined instructions of a microprocessor instruction set and a control unit for interpreting the instructions and for controlling the logic units accordingly. An internal timer of the microprocessor is activated by the control unit in response to the execution of a dedicated standby instruction of the microprocessor instruction set. Responsive thereto, a timeout signal is delivered to the control unit so as to place the microprocessor in a standby state during a determined timeout period.
    Type: Application
    Filed: March 17, 2005
    Publication date: September 29, 2005
    Applicant: STMicroelectronics S.A.
    Inventors: Olivier Ferrand, Jean-Michel Gril-Maffre
  • Patent number: 6913198
    Abstract: A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: July 5, 2005
    Assignee: STMicroelectronics SA
    Inventors: Ludovic Ruat, Olivier Ferrand, Bruno Gailhard
  • Publication number: 20050034016
    Abstract: A microcontroller includes a microprocessor (2), a reset circuit (3) selectively generating a signal for resetting the microprocessor (2), and a detection device (4), having at least one input for receiving (5) a vital logic signal from the microcontroller and an output (6) applying a reset command to the reset circuit upon detecting a change in the logic state of the vital logic signal. A computer system can include one or more of the microcontroller.
    Type: Application
    Filed: July 2, 2004
    Publication date: February 10, 2005
    Applicant: STMICROELECTRONICS S.A.
    Inventors: Olivier Ferrand, Dragos Davidescu
  • Publication number: 20040226999
    Abstract: A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.
    Type: Application
    Filed: June 22, 2004
    Publication date: November 18, 2004
    Applicant: STMicroelectronics SA
    Inventors: Ludovic Ruat, Olivier Ferrand, Bruno Gailhard
  • Patent number: 6772946
    Abstract: A smart card reader includes a housing for receiving a smart card, a microprocessor, and a connector for connecting the microprocessor to the received smart card for establishing communications therebetween. A voltage source provides a power supply voltage to the microprocessor based upon the smart card being received in the housing. The smart card reader further includes a first switch interposed between the voltage source and a power supply terminal of the microprocessor. The first switch is closed when the received smart card is at an end of travel in the housing so that the power supply voltage is provided to the microprocessor, and is opened when the received smart card is no longer at the end of travel in the housing so that the power supply voltage is not provided to the microprocessor.
    Type: Grant
    Filed: January 29, 2002
    Date of Patent: August 10, 2004
    Assignee: STMicroelectronics SA
    Inventors: Ludovic Ruat, Olivier Ferrand, Bruno Gailhard
  • Patent number: 6759893
    Abstract: A temperature-compensated current source includes a first arm fixing a reference voltage, a second arm fixing a reference current, and a third arm providing an output current obtained by copying the reference current in a first current mirror. A second current mirror copies, in the voltage reference arm, the reference current while a voltage copying circuit copies the reference voltage at a node of the second arm connected to ground by a first resistor series-connected with n parallel-connected diodes. A second resistor is parallel-connected with the assembly formed by the first resistor series-connected with the n parallel-connected diodes.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: July 6, 2004
    Assignee: STMicroelectronics SA
    Inventors: Bruno Gailhard, Olivier Ferrand
  • Patent number: 6731178
    Abstract: A generator includes an oscillator for producing a clock signal from an N-bit control number. The oscillator includes a first group of cells, with each cell including at least one series connected inverter. A first selection circuit selects a variable number of the cells as a function of the most significant bits of the control number. The oscillator also includes a second group of cells, with each cell including at least one series connected inverter. A second selection circuit selects one of the cells as a function of the least significant bits of the control number. The selected cells of the first and second groups of cells are series connected to form a chain of inverters.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: May 4, 2004
    Assignee: STMicroelectronics SA
    Inventors: Bruno Gailhard, Olivier Ferrand