Abstract: A rivet for blind fastening may include a screw with a handling element, a break groove, a head separated from the handling element by the break groove, and a threaded part; a sleeve with a collar and a tubular shank comprising an internal thread intended to come into engagement with the threaded part of the screw. The handling element comprises a first handling portion able to guide the introduction of the rivet in a setting tool, and a second handling portion able to transmit a torque, the two handling portions being separated by blocking portion able to limit an axial movement of the rivet in a setting tool. A setting nose for installing such a rivet, and a setting method are also described. These in particular are applicable to the assembly of aircraft structures.

Abstract: Embodiments of the invention are directed to control devices configured for use with computing devices. More specifically, the present invention relates to methods and devices for shortening wireless reconnection time by determining the presence of an object or body near a device. When the control device detects an object or body in proximity to the device, the control device may automatically establish a wireless connection with a host devices, such that when the control device receives any user interactions, the wireless connection has already been established, preventing loss of data.

Abstract: The present invention relates to a discrete transform calculation device (FFTP). The device has control means (CNTRL) which configure first and second memories (RAM1 and RAM2) according to the number of transforms used during a first processing. The device applies in particular to a demodulator which allows management of several Fourier transforms in parallel.

Abstract: A method and a demodulator for processing a Fast Fourier Transform using data blocks include a Fast Fourier Transform (FFT) coprocessor and a digital signal processor (DSP). The FFT coprocessor includes a start function and a computation function (F_FFT). The start function is adapted to generate a start signal each time a first data of a new block is received. The DSP includes a time error function which indicates to the start function for how much data it has to wait before a new start signal is generated.

Abstract: The invention presents a programmable communication system for generating data for at least one processing unit at a fixed symbol frequency, which lies within a range of frequencies, on the basis of input samples received at an input frequency higher than the symbol frequency. To achieve this, communication time slots are reserved periodically as a function of the maximum envisaged symbol frequency, and the device is designed for using only a fraction of these slots reserved as a function of the fixed symbol frequency for transmitting the generated data. The invention is applicable to broadband digital communications, digital television, channel decoding, demodulation and other similar technology areas.

Abstract: The invention relates to a calculation method of a cumulative histogram. Such a method comprises calculation stages in which at least two additions are used in parallel. Each addition permits to calculate an addition result. The additions are made either with two histogram values or with one histogram value and one addition result calculated during a previous calculation stage, or with two addition results calculated during one or two previous calculation stages.

Abstract: The invention offers a method of calculating digital filters enabling to multiplex various different filters with the aid of a programmable co-processor circuit comprising a calculation element and memory registers. The invention comprises making an anticipated calculation of part of the result of the current filter before the last data included in the calculation of this result has arrived. For this purpose, successive products between predetermined filter coefficients and the corresponding input data which have already been used for the calculation of the preceding results are accumulated in an iterative fashion in an intermediate result in order to anticipate the calculation of the current result. The calculation of the last intermediate result for each final result is triggered each time a new input data is received, so that each filter result is immediately available once the last input data involved in this result has been received.

Abstract: A device provides a normally static and nevertheless programmable architecture, for example, a programmable digital demodulator. The device includes a first and a second processor module. The second module receives data and instructions and executes operations for obtaining a result. The first module transmits instructions to the second module according to a predetermined scheme, each instruction indicating the operation it is provided to execute in the current time slot. An operation is only executed by the second module if the necessary data are available. It is not possible to execute a different operation from the one that is provided in the current time slot. Thus, no result can be delivered outside the time slots provided for this purpose.

Abstract: The invention relates to a multi-standard digital receiver, in a digital video transmission system. It comprises a channel decoder for protecting a transmitted signal against channel transmission errors, the channel decoder comprising: a set of co-processors including at least 3 clusters of programmable co-processors for executing the functions of a digital front-end block (DFE), a channel correction block (CHN) and a forward error correction block (FEC), respectively, a general purpose processor (DSP) for managing control, synchronization and configuration of the channel decoder, and a memory (SM) shared between the clusters and the general purpose processor.

Abstract: The invention provides a programmable network architecture for interconnecting several calculation modules in a receiver of a data transmission system with a very high data rate, which receiver comprises a forward and a return communication path. The architecture renders it possible to realize local communications between neighboring calculation modules and global communications between non-neighboring calculation modules. The network is formed by a sequence of programmable interconnection cells comprising memory means for storing the data which traverse between two non-neighboring modules which are present in the forward path and the return path, respectively. The role of these memories is to guarantee that the data pass through at most two successive multiplexers in one clock cycle, so that a high clock speed can be chosen.

Abstract: The invention relates to a processing device for digital data which is capable of processing data which have been sampled with a sampling clock which may have any value whatsoever with respect to the basic clock of the device. To achieve this, the device is provided with means for generating from its basic clock an operational clock which is a function of the sampling clock of the data to be processed. This operational clock has a constant integer number of active periods during one cycle of the sampling clock. Application: Digital communication systems, especially demodulation.

Abstract: The invention relates to a digital demodulator whose architecture is adapted to multicarrier modulations (radio wave transmissions), but which remains suitable for use for monocarrier modulations (cable and satellite transmissions). With multicarrier modulations, the demodulator must carry out certain functions at a frequency of the order of sampling frequency and other functions at a frequency of the order of the symbol frequency. The invention comprises a separation of the architecture into three modules: a first module which carries out programs which are repeated with a first frequency, a second module capable of using programs which are repeated with a second frequency, and an interface module between the first and the second module. An advantage is that the memory size necessary for storing instructions for the first module is reduced. An application is for DVB standard transmission of digital TV programs.

Abstract: The present invention relates to a discrete transform calculation device (FFTP). The device has control means (CNTRL) which configure first and second memories (RAM1 and RAM2) according to the number of transforms used during a first processing. The device applies in particular to a demodulator which allows management of several Fourier transforms in parallel.

Abstract: A component architecture for digital signal processing is presented. A two dimensional reconfigureable array of identical processors, where each processor communicates with its nearest neighbors, provides a simple and power-efficient platform to which convolutions, finite impulse response (“FIR”) filters, and adaptive finite impulse response filters can be mapped. An adaptive FIR can be realized by downloading a simple program to each cell. Each program specifies periodic arithmetic processing for local tap updates, coefficient updates, and communication with nearest neighbors. During steady state processing, no high bandwidth communication with memory is required.

Abstract: The invention relates to a device (FFTP) for computing discrete transforms. The device comprises a local memory (RAM2) for registering results of sub-transform computations, a sub-transform computation comprising several computation layers. The device is characterized by computation means (CAL_M) which are capable of interlacing computation layers of two or several consecutive sub-transforms of the same size.

Abstract: The present invention relates to a method and a demodulator for processing a Fast Fourier Transform using data blocks. The invention is characterized in that it comprises a Fast Fourier Transform coprocessor (FFT_P) and a digital signal processor (DSP). Said coprocessor (FFT_P) comprises a start function (F_STRT) and a computation function (F_FFT). Said start function (F_STRT) is adapted to send to said computation function (F_FFT) a start signal (S_STRT) each time a first data (D) of a new block is received. Said digital signal processor (DSP) comprises a time error function (F_TMERR), which indicates to the start function (F_STRT) for how much data it has to wait before a new start signal (S_STRT) is sent.

Abstract: The invention relates to a multi-standard digital receiver, in a digital video transmission system.

Abstract: The invention relates to a device which comprises a first and a second processor module. The second module M2 is intended to receive data and instructions and to execute operations for obtaining a result. The first module is intended to transmit instructions to the second module according to a predetermined scheme, each instruction indicating the operation it is provided to execute in the current time slot.

Abstract: A memory system is disclosed. The memory system provides for input data (datain_B and datain_F) and for taps (w_in) and is partitioned into various segments. The memory system includes means for recombining the segments in order to be adapted to different filters. In one embodiment, with the total dimension of the memory being 2L, the memory system includes six partitions having respective dimensions 2L/5, 4L/15, L/3, L/5, 2L/15, 2L/3, between which the data and taps are distributed by means of multiplexers.

Abstract: An apparatus having plurality of filter processing elements is provided in order to obtain adequate calculation power, particularly to enable a plurality of filters to be calculated by multiplexing. The calculation of a filter is effected in a plurality of iterations; a filter section is calculated in each iteration while the same operator is used for iteratively calculating a plurality of operations and a plurality of multiplexed filters; in each iteration a plurality of data sets is used. Each filter processing element comprises a number of partial-result registers (y-data) equal to the number of filters that can be multiplexed. Each register has a write input connected to the output (y) of a final adder and each register has a read output connected to one of the inputs (y-old) of the final adder.