Patents by Inventor Olivier Pribetich

Olivier Pribetich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9754072
    Abstract: One aspect checks and prepares design data (202) based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation (204) is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s), without performing additional design rule checking on the design rule(s). Additional physical implementation (206) may be optionally performed for portion(s) of the electronic design not implemented with the structured physical implementation. Layout fixing or optimization may be optionally performed to fix design rule violations in the additional physical implementation results, if any, or to optimize the additional physical implementation results.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 5, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jeffrey S. Salowe, Satish Raj, Olivier Pribetich, Karun Sharma, Yinnie Lee, Gary Matsunami
  • Patent number: 9384317
    Abstract: One aspect checks and prepares design data (202) based on design rule(s) to identify tracks for physical implementation of an electronic design. Structured physical implementation (204) is performed to implement at least a part of the electronic design by using the tracks under separate design rule(s). Structured physical implementation using the tracks under separate design rules result in correct-by-construction implementation results automatically satisfying the design rule(s), without performing additional design rule checking on the design rule(s). Additional physical implementation (206) may be optionally performed for portion(s) of the electronic design not implemented with the structured physical implementation. Layout fixing or optimization may be optionally performed to fix design rule violations in the additional physical implementation results, if any, or to optimize the additional physical implementation results.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: July 5, 2016
    Assignee: Cadence Design Systems, Inc.
    Inventors: Jeffrey S. Salowe, Satish Raj, Olivier Pribetich, Karun Sharma, Yinnie Lee, Gary Matsunami
  • Patent number: 8807948
    Abstract: Systems and methods for real-time design checking of an integrated circuit design, include the operations of receiving at a design tool, design elements of an integrated circuit design entered by an integrated circuit designer; the design tool performing real-time design checks on the design elements as they are entered by the integrated circuit designer to determine whether a design element violates a design rule; when the design tool detects a violation of a design rule based on the design checks alerting the integrated circuit designer; and the design tool presenting a correction to correct the violation of the design rule. The real-time design checks can include, comparing each design element to one or more known non-compliant design elements stored in a database to determine whether a non-compliant design element was entered or is being entered by the integrated circuit designer.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: August 19, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wilbur Luo, Olivier Pribetich, Olivier Omedes, Roland Ruehl, Ya-Chieh Lai, Frank E. Gennari
  • Patent number: 8543965
    Abstract: Various embodiments are directed at methods and systems for implementing automatic fixing of a layout, implementing fuzzy pattern replacement, and implementing pattern capturing in a layout of an electronic circuit design. Various processes or modules comprise the act or module of identifying a first pattern from within an electronic circuit layout. The processes or modules also comprise identifying a fixing process or a replacement pattern for the first pattern and the act of performing pattern replacement or pattern fixing on the first pattern. The processes or modules may further comprise the act or module of searching the layout for patterns that match the first pattern, and the act or module of performing pattern replacement of pattern fixing on the patterns that match the first pattern. Some embodiments are also directed at articles of manufacture embodying a sequence of instructions for implementing the processes described here.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: September 24, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ya-Chieh Lai, Frank Gennari, Olivier Omedes, Olivier Pribetich
  • Patent number: 8516406
    Abstract: Various embodiments are directed at methods and systems for implementing automatic fixing of a layout, implementing fuzzy pattern replacement, and implementing pattern capturing in a layout of an electronic circuit design. Various processes or modules comprise the act or module of identifying a first pattern from within an electronic circuit layout. The processes or modules also comprise identifying a fixing process or a replacement pattern for the first pattern and the act of performing pattern replacement or pattern fixing on the first pattern. The processes or modules may further comprise the act or module of searching the layout for patterns that match the first pattern, and the act or module of performing pattern replacement of pattern fixing on the patterns that match the first pattern. Some embodiments are also directed at articles of manufacture embodying a sequence of instructions for implementing the processes described here.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: August 20, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ya-Chieh Lai, Frank Gennari, Olivier Omedes, Olivier Pribetich
  • Patent number: 8429582
    Abstract: Various embodiments are directed at methods and systems for implementing automatic fixing of a layout, implementing fuzzy pattern replacement, and implementing pattern capturing in a layout of an electronic circuit design. Various processes or modules comprise the act or module of identifying a first pattern from within an electronic circuit layout. The processes or modules also comprise identifying a fixing process or a replacement pattern for the first pattern and the act of performing pattern replacement or pattern fixing on the first pattern. The processes or modules may further comprise the act or module of searching the layout for patterns that match the first pattern, and the act or module of performing pattern replacement of pattern fixing on the patterns that match the first pattern. Some embodiments are also directed at articles of manufacture embodying a sequence of instructions for implementing the processes described here.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: April 23, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ya-Chieh Lai, Frank Gennari, Olivier Omedes, Olivier Pribetich
  • Publication number: 20130086541
    Abstract: Systems and methods for real-time design checking of an integrated circuit design, include the operations of receiving at a design tool, design elements of an integrated circuit design entered by an integrated circuit designer; the design tool performing real-time design checks on the design elements as they are entered by the integrated circuit designer to determine whether a design element violates a design rule; when the design tool detects a violation of a design rule based on the design checks alerting the integrated circuit designer; and the design tool presenting a correction to correct the violation of the design rule. The real-time design checks can include, comparing each design element to one or more known non-compliant design elements stored in a database to determine whether a non-compliant design element was entered or is being entered by the integrated circuit designer.
    Type: Application
    Filed: September 29, 2011
    Publication date: April 4, 2013
    Inventors: Wilbur Luo, Olivier Pribetich, Olivier Omedes, Roland Ruehl, Ya-Chieh Lai, Frank E. Gennari
  • Patent number: 6233723
    Abstract: The present invention provides stimuli generators, methods of analyzing a cell, methods of generating at least one stimuli, and methods of characterizing delay of a cell. One method of analyzing a cell in accordance with the invention includes providing a truth table which includes plural lines defining the logical behavior of a cell, the truth table comprising stimulus for application to the cell and output information generated by the cell responsive to applied stimulus; providing a preselected condition; and selectively extracting at least one stimuli from the truth table responsive to the preselected condition.
    Type: Grant
    Filed: August 28, 1997
    Date of Patent: May 15, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Olivier Pribetich
  • Patent number: 5416719
    Abstract: A computerized method of generating a truth table of a cell in a library of circuit cells includes representing basic elements of the cells in a hardware description language, representing each cell as a set of equations in that language and parsing the equations each in accordance with a respective abstract data tree of which the `leaves` or extremities are signal values or constants. The parsing of each equation yields a respective partial truth table. The partial truth tables are merged to provide a complete truth table, which is preferably subjected to Boolean and/or expression optimization to reduce the number of entries in the truth table.
    Type: Grant
    Filed: December 17, 1992
    Date of Patent: May 16, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Olivier Pribetich