Abstract: A first input signal that corresponds to an output transmitted signal of an amplifier of a vehicle radar system is received and a digital threshold signal is transmitted to an input terminal of a digital-to-analog converter. The digital-to-analog converter is configured to generate an analog threshold value that is at least partially determined by a digital threshold value encoded into the digital threshold signal. If it is determined that a magnitude of the first input signal is less than a magnitude of the analog threshold value, a flag signal is transmitted to a system controller. The flag signal is indicative that a power level of the first output signal has fallen below a safety threshold value.

Abstract: Disclosed are various embodiments for improving the accuracy of a phase associated with the radar signal by identifying a spectral signature associated with a radio frequency (RF) impairment and performing digital predistortion to enhance the radar performance and to compensate for the impairment that causes offset or imbalance of the phase rotator output cause signal distortion or otherwise degrade of the phase of the signal. The self-calibrating mechanism of the present disclosure is configured to identify the impairments, determine a spectral signature associated with the impairment, and optimize the phase error through digital predistortion of the RF signal based at least in part on the spectral signature associated with the impairment.

Abstract: A phase rotator calibration system is provided. The phase rotator calibration system includes a phase rotator portion having input for receiving an input signal and an output for providing an output signal. A calibration portion is coupled to the phase rotator portion. The calibration portion is configured to determine a phase error based on a phase estimation. The phase estimation is generated by way of an arccosine function.

Abstract: Multi-channel radio frequency (RF) transmitter (100) and method of calibrating the transmitter are provided.

Abstract: There is described a method of determining phase error caused by impairments in a phase rotator, said impairments including leakage in mixers and/or multipliers of the phase rotator, gain/amplitude imbalance and a known phase imbalance between an I path and a Q path in the phase rotator, the phase rotator having an input for receiving a reference phase value, a local oscillator and circuitry configured to provide an output signal with a phase corresponding to the reference phase value.

Abstract: A phase rotator calibration system is provided. The phase rotator calibration system includes a phase rotator portion having input for receiving an input signal and an output for providing an output signal. A calibration portion is coupled to the phase rotator portion. The calibration portion is configured to determine a phase error based on a phase estimation. The phase estimation is generated by way of an arccosine function.

Abstract: A method for synchronizing a cascaded RADAR system (80) includes modulating (320) with a master RADAR system (12), an amplitude of a sequence of clock cycles of a clock (70) in response to a Ramp Frame Start (RFS) signal (92). The master RADAR system determines (322) a duration (310, 312, 314) of the sequence of clock cycles based on a code. A slave RADAR system (14) demodulates (324) the sequence of clock cycles to recover the clock and the RFS signal, wherein a clock leading edge of the clock is phase aligned to an RFS leading edge of the RFS signal. The slave RADAR system decodes (326) the code from the duration of the sequence of clock cycles, wherein the code determines an action performed by the slave RADAR system in response to receiving a data signal from the master RADAR system.

Abstract: Disclosed are various embodiments for improving the accuracy of a phase associated with the radar signal by identifying a spectral signature associated with a radio frequency (RF) impairment and performing digital predistortion to enhance the radar performance and to compensate for the impairment that causes offset or imbalance of the phase rotator output cause signal distortion or otherwise degrade of the phase of the signal. The self-calibrating mechanism of the present disclosure is configured to identify the impairments, determine a spectral signature associated with the impairment, and optimize the phase error through digital predistortion of the RF signal based at least in part on the spectral signature associated with the impairment.

Abstract: Multi-channel radio frequency (RF) transmitter (100) and method of calibrating the transmitter are provided.

Abstract: A Time to Digital converter (TDC) may have a Vernier architecture of multiple successive modules arranged in series. Each of the modules may output an indication of a differential in phase between two received signals. Each module may include two signal lines for the received signals, and it may be desirable to calibrate the two signal lines. To this end, a signal output from a proceeding module may be provided to both signal lines of a succeeding module and used as a reference or calibration signal to calibrate the two signal lines of the module.

Abstract: A method for synchronizing a cascaded RADAR system (80) includes modulating (320) with a master RADAR system (12), an amplitude of a sequence of clock cycles of a clock (70) in response to a Ramp Frame Start (RFS) signal (92). The master RADAR system determines (322) a duration (310, 312, 314) of the sequence of clock cycles based on a code. A slave RADAR system (14) demodulates (324) the sequence of clock cycles to recover the clock and the RFS signal, wherein a clock leading edge of the clock is phase aligned to an RFS leading edge of the RFS signal. The slave RADAR system decodes (326) the code from the duration of the sequence of clock cycles, wherein the code determines an action performed by the slave RADAR system in response to receiving a data signal from the master RADAR system.

Abstract: A digital synthesizer includes a ramp generator that generates a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; a digitally controlled oscillator, DCO, that receives the FCW signal and outputs a DCO signal; and a feedback loop that includes a dual time-to-digital converter, TDC, circuit to measure a delay between a representation of the DCO signal and a reference signal. The TDC circuit comprises a medium-resolution TDC circuit coupled to a fine-resolution TDC circuit; and a phase comparator coupled to the ramp generator that compares a phase of the FCW signal output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The medium-resolution TDC circuit comprises a plurality of individual delay cells, where each of the plurality of individual delay cells is coupled to a respective individual fine-resolution TDC circuit.

Abstract: A device comprising: a voltage reference supply, configured to provide a reference voltage that varies in response to temperature according to a predefined relationship; a temperature sensor providing a temperature signal indicating a temperature; a first controller configured to receive the temperature signal and to output a control signal; an LC-DCO receiving the reference voltage and providing an output signal with a frequency from an LC circuit, the LC-DCO comprising a switched capacitor bank configured to provide temperature compensation by varying an effective capacitance in the LC circuit in response to the control signal.

Abstract: A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; a digitally controlled oscillator, DCO configured to receive the FCW signal; a feedback loop; and a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The digital synthesizer comprises a gain circuit coupled to a multiplier located between the ramp generator and the DCO and configured to apply at least one gain from a plurality of selectable gains to the N-bit oscillator control signal that set a selectable loop gain of the digital synthesizer and thereby set a selectable loop bandwidth; and calculate and apply a gain offset dependent upon the selected gain that is adapted when the selected gain is changed.

Abstract: A digital synthesizer is described that comprises: a digitally controlled oscillator, DCO; a feedback loop; a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; and a phase comparator configured to compare a phase of the FCW output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The digital synthesizer comprises a gain circuit coupled to a multiplier located between the ramp generator and the DCO and configured to apply a frequency-dependent gain signal to the N-bit oscillator control signal to maintain an open loop gain of the all-digital phase locked loop, ADPLL, and a PLL loop bandwidth that is substantially constant across a frequency modulation bandwidth.

Abstract: A method of calibrating a digitally controlled oscillator (DCO). The method comprises configuring a fine tuning capacitive component of the DCO into a minimum capacitance configuration therefor, configuring a coarse tuning capacitive component of the DCO into a first configuration therefor and determining a resulting first output frequency of the DCO.

Abstract: A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words (FCW), that describes a desired frequency modulated continuous wave; a digitally controlled oscillator (DCO) configured to receive the FCW signal and generate a DCO output signal; a feedback loop comprising a time-to-digital converter (TDC), wherein the feedback loop is configured to feed back the DCO output signal; a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW signal output from the ramp generator with the DCO output signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal in response thereto. The TDC receives a representation of the DCO output signal and a reference frequency signal to sample the DCO output signal and outputs multiple selectable delays of the DCO output signal.

Abstract: A device comprising: a voltage reference supply, configured to provide a reference voltage that varies in response to temperature according to a predefined relationship; a temperature sensor providing a temperature signal indicating a temperature; a first controller configured to receive the temperature signal and to output a control signal; an LC-DCO receiving the reference voltage and providing an output signal with a frequency from an LC circuit, the LC-DCO comprising a switched capacitor bank configured to provide temperature compensation by varying an effective capacitance in the LC circuit in response to the control signal.

Abstract: A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; a digitally controlled oscillator, DCO, configured to receive the FCW signal and output a DCO signal; and a feedback loop that includes a dual time-to-digital converter, TDC, circuit configured to measure a delay between a representation of the DCO signal and a reference signal. The TDC circuit comprises a medium-resolution TDC circuit coupled to a fine-resolution TDC circuit; and a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW signal output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The medium-resolution TDC circuit comprises a plurality of individual delay cells, where each of the plurality of individual delay cells is coupled to a respective individual fine-resolution TDC circuit.

Abstract: A Time to Digital converter (TDC) may have a Vernier architecture of multiple successive modules arranged in series. Each of the modules may output an indication of a differential in phase between two received signals. Each module may include two signal lines for the received signals, and it may be desirable to calibrate the two signal lines. To this end, a signal output from a proceeding module may be provided to both signal lines of a succeeding module and used as a reference or calibration signal to calibrate the two signal lines of the module.