Patents by Inventor Oluwatobi AJILA
Oluwatobi AJILA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220382576Abstract: A snapshot handler is registered with an event monitoring subsystem of a process virtual machine, the registering specifying a trigger event of the snapshot handler, wherein the trigger event comprises execution of a specified portion of an application executing in the process virtual machine, the trigger event specified externally from a source code of the application. Responsive to the event monitoring subsystem detecting an occurrence of the trigger event, the snapshot handler is executed, storing data of an execution state of the process virtual machine at a time of occurrence of the trigger event.Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Applicant: International Business Machines CorporationInventors: Oluwatobi Ajila, DANIEL HEIDINGA
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Patent number: 11500661Abstract: A snapshot handler is registered with an event monitoring subsystem of a process virtual machine, the registering specifying a trigger event of the snapshot handler, wherein the trigger event comprises execution of a specified portion of an application executing in the process virtual machine, the trigger event specified externally from a source code of the application. Responsive to the event monitoring subsystem detecting an occurrence of the trigger event, the snapshot handler is executed, storing data of an execution state of the process virtual machine at a time of occurrence of the trigger event.Type: GrantFiled: August 26, 2020Date of Patent: November 15, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oluwatobi Ajila, Daniel Heidinga
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Publication number: 20220283785Abstract: A computer-implemented method for bytecode class verification includes: encountering a class requiring verification of its bytecode during a run of an application; determining whether class relationship data for the class exists in a shared classes cache; in response to a determination that the class relationship data for the class does not exist in the shared classes cache: performing a linear bytecode walk of the bytecode to identify relationship data for the class and verify that the bytecode is well-formed; and storing the identified relationship data as the class relationship data for the class in the shared classes cache; in response to a determination that the class relationship data for the class does exist in the shared classes cache: retrieving the class relationship data for the class from the shared classes cache; and processing the class relationship data.Type: ApplicationFiled: May 27, 2022Publication date: September 8, 2022Inventors: Sharon WANG, Daniel HEIDINGA, Hang SHAO, Oluwatobi AJILA, Graham CHAPMAN
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Patent number: 11403075Abstract: A computer-implemented method for bytecode class verification includes: encountering a class requiring verification of its bytecode during a run of an application; determining whether class relationship data for the class exists in a shared classes cache; in response to a determination that the class relationship data for the class does not exist in the shared classes cache: performing a linear bytecode walk of the bytecode to identify relationship data for the class and verify that the bytecode is well-formed; and storing the identified relationship data as the class relationship data for the class in the shared classes cache; in response to a determination that the class relationship data for the class does exist in the shared classes cache: retrieving the class relationship data for the class from the shared classes cache; and processing the class relationship data.Type: GrantFiled: November 25, 2019Date of Patent: August 2, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sharon Wang, Daniel Heidinga, Hang Shao, Oluwatobi Ajila, Graham Chapman
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Publication number: 20220066805Abstract: A snapshot handler is registered with an event monitoring subsystem of a process virtual machine, the registering specifying a trigger event of the snapshot handler, wherein the trigger event comprises execution of a specified portion of an application executing in the process virtual machine, the trigger event specified externally from a source code of the application. Responsive to the event monitoring subsystem detecting an occurrence of the trigger event, the snapshot handler is executed, storing data of an execution state of the process virtual machine at a time of occurrence of the trigger event.Type: ApplicationFiled: August 26, 2020Publication date: March 3, 2022Applicant: International Business Machines CorporationInventors: Oluwatobi Ajila, Daniel Heidinga
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Patent number: 11221867Abstract: Resolving segmented constant pools in a virtual machine managed runtime. An embodiment includes allocating, using one or more processors of a computing device, for each specialization created in a class of specializations, a constant pool (CP) cache, assigning an owner to each segment of constant pools, maintaining, in a memory of the computing device, a list of specializations in the class, and copying, upon determining that a CP segment entry visible to the specialization is resolved in the owner, the entry to a specializations cache of the memory. An embodiment includes assigning a new specialized CP segment as an owner of that CP segment and adding a new entry associated with the new specialization to a template class owners table, retrieving, based on looking for entry at runtime, a slot pointed to in the owners table and resolving the CP entry in the constant pool cache of the owner.Type: GrantFiled: January 2, 2020Date of Patent: January 11, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oluwatobi Ajila, Daniel Heidinga
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Patent number: 11188316Abstract: An embodiment includes executing a code interpretation engine such that the interpretation engine interprets a first portion of a source code that includes a first comparison between a first pair of operands. The embodiment also includes performing, in memory, a first bitwise comparison between a block A1 and a block B1 of the first portion of the source code. The embodiment also speeds up execution of the first portion of the source code responsive to the first bitwise comparison producing a negative result. The embodiment speeds up the first portion by omitting at least one of (i) a second bitwise comparison between a block A2 and a block B2, and (ii) a field-wise comparison between a block A3 and a block B3.Type: GrantFiled: March 9, 2020Date of Patent: November 30, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Oluwatobi Ajila, Andrew James Craik, Daniel Heidinga, Graham Alan Chapman
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Publication number: 20210279044Abstract: An embodiment includes executing a code interpretation engine such that the interpretation engine interprets a first portion of a source code that includes a first comparison between a first pair of operands. The embodiment also includes performing, in memory, a first bitwise comparison between a block A1 and a block B1 of the first portion of the source code. The embodiment also speeds up execution of the first portion of the source code responsive to the first bitwise comparison producing a negative result. The embodiment speeds up the first portion by omitting at least one of (i) a second bitwise comparison between a block A2 and a block B2, and (ii) a field-wise comparison between a block A3 and a block B3.Type: ApplicationFiled: March 9, 2020Publication date: September 9, 2021Applicant: International Business Machines CorporationInventors: Oluwatobi Ajila, Andrew James Craik, Daniel Heidinga, Graham Alan Chapman
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Publication number: 20210208914Abstract: Resolving segmented constant pools in a virtual machine managed runtime. An embodiment includes allocating, using one or more processors of a computing device, for each specialization created in a class of specializations, a constant pool (CP) cache, assigning an owner to each segment of constant pools, maintaining, in a memory of the computing device, a list of specializations in the class, and copying, upon determining that a CP segment entry visible to the specialization is resolved in the owner, the entry to a specializations cache of the memory. An embodiment includes assigning a new specialized CP segment as an owner of that CP segment and adding a new entry associated with the new specialization to a template class owners table, retrieving, based on looking for entry at runtime, a slot pointed to in the owners table and resolving the CP entry in the constant pool cache of the owner.Type: ApplicationFiled: January 2, 2020Publication date: July 8, 2021Applicant: International Business Machines CorporationInventors: Oluwatobi Ajila, daniel Heidinga
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Publication number: 20210157552Abstract: A computer-implemented method for bytecode class verification includes: encountering a class requiring verification of its bytecode during a run of an application; determining whether class relationship data for the class exists in a shared classes cache; in response to a determination that the class relationship data for the class does not exist in the shared classes cache: performing a linear bytecode walk of the bytecode to identify relationship data for the class and verify that the bytecode is well-formed; and storing the identified relationship data as the class relationship data for the class in the shared classes cache; in response to a determination that the class relationship data for the class does exist in the shared classes cache: retrieving the class relationship data for the class from the shared classes cache; and processing the class relationship data.Type: ApplicationFiled: November 25, 2019Publication date: May 27, 2021Inventors: Sharon WANG, Daniel HEIDINGA, Hang SHAO, Oluwatobi AJILA, Graham CHAPMAN
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Patent number: 10678482Abstract: Aspects provide multi-tier data synchronization based on a concurrent linked monitor list. A computer processor associates each of different data regions of a packed data object with different mutual exclusion monitor nodes of a linked list, the data regions defined by a data offset location within memory data and a length of the data region from the offset. In response to determining that a first data region of the packed data object is on-heap memory, the processor associates the first data region with a container representative of the linked list sorted in ascending order of the respective offset values, and a hash code of the container; and in response to determining that a second data region of the packed data object is off-heap memory, stores container information for the second data region in the linked list and resorts the linked-list nodes of container information in ascending order of offset values.Type: GrantFiled: July 24, 2018Date of Patent: June 9, 2020Assignee: International Business Machines CorporationInventors: Oluwatobi A. Ajila, Eric Aubanel, Kenneth B. Kent, Angela Lin, Bing Yang
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Publication number: 20180329641Abstract: Aspects provide multi-tier data synchronization based on a concurrent linked monitor list. A computer processor associates each of different data regions of a packed data object with different mutual exclusion monitor nodes of a linked list, the data regions defined by a data offset location within memory data and a length of the data region from the offset. In response to determining that a first data region of the packed data object is on-heap memory, the processor associates the first data region with a container representative of the linked list sorted in ascending order of the respective offset values, and a hash code of the container; and in response to determining that a second data region of the packed data object is off-heap memory, stores container information for the second data region in the linked list and resorts the linked-list nodes of container information in ascending order of offset values.Type: ApplicationFiled: July 24, 2018Publication date: November 15, 2018Inventors: OLUWATOBI A. AJILA, Eric Aubanel, Kenneth B. Kent, Angela Lin, Bing Yang
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Patent number: 10073646Abstract: Aspects provide multi-tier data synchronization based on a concurrent linked monitor list. A computer processor associates each of different data regions of a packed data object with different mutual exclusion monitor nodes of a linked list, the data regions defined by a data offset location within memory data and a length of the data region from the offset. In response to determining that a first data region of the packed data object is on-heap memory, the processor associates the first data region with a container representative of the linked list sorted in ascending order of the respective offset values, and a hash code of the container; and in response to determining that a second data region of the packed data object is off-heap memory, stores container information for the second data region in the linked list and resorts the linked-list nodes of container information in ascending order of offset values.Type: GrantFiled: January 31, 2017Date of Patent: September 11, 2018Assignee: International Business Machines CorporationInventors: Oluwatobi A. Ajila, Eric Aubanel, Kenneth B. Kent, Angela Lin, Bing Yang
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Patent number: 10061570Abstract: In an approach for removing tenant initialization check per tenant for compiled code, a processor receives a request to create a tenant. A processor creates the tenant. A processor marks a current thread of the tenant as not eligible to run just-in-time (JIT) code, wherein the marking indicates that when a method is invoked, a non-JIT version of the method is executed. A processor executes initialization of a first class from an optimization list, wherein the optimization list is a configurable list of classes to be initialized prior to running JIT code. A processor determines that class initialization has been executed for all classes on the optimization list. A processor adjusts the marking to indicate that the current thread is eligible to run JIT code and that the tenant may run JIT code that assumes, without checking, that classes on the optimization list are initialized.Type: GrantFiled: September 30, 2016Date of Patent: August 28, 2018Assignee: International Business Machines CorporationInventors: Oluwatobi A. Ajila, Graham A. Chapman, Michael H. Dawson, San Hong Li, Hui Shi
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Publication number: 20180217776Abstract: Aspects provide multi-tier data synchronization based on a concurrent linked monitor list. A computer processor associates each of different data regions of a packed data object with different mutual exclusion monitor nodes of a linked list, the data regions defined by a data offset location within memory data and a length of the data region from the offset. In response to determining that a first data region of the packed data object is on-heap memory, the processor associates the first data region with a container representative of the linked list sorted in ascending order of the respective offset values, and a hash code of the container; and in response to determining that a second data region of the packed data object is off-heap memory, stores container information for the second data region in the linked list and resorts the linked-list nodes of container information in ascending order of offset values.Type: ApplicationFiled: January 31, 2017Publication date: August 2, 2018Inventors: OLUWATOBI A. AJILA, ERIC AUBANEL, ANGELA LIN, KENNETH B. KENT, BING YANG
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Publication number: 20180203853Abstract: A method, computer program product, and system includes a processor(s) generating an interface to enable communication of data elements from a first computing resource to a second computing resource. An element of the data is a data structure of variable size. To generate the interface, the processor(s) requests a layout that includes a variable array. The processor(s) locates a layout referenced by the variable array; the layout for the variable array can accommodate the data structure of variable size. The processor(s) generates the layout, which includes generating a runtime class for an element type of the data structure of variable size and generating a runtime class for the variable array. The processor generates an enclosing layout that indicates to the second computing resource, delineations between the data elements. The processor(s) communicates, via the interface, the data elements from the first computing resource to the second computing resource.Type: ApplicationFiled: January 13, 2017Publication date: July 19, 2018Inventors: Oluwatobi A. AJILA, Daniel J. HEIDINGA
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Publication number: 20170017474Abstract: In an approach for removing tenant initialization check per tenant for compiled code, a processor receives a request to create a tenant. A processor creates the tenant. A processor marks a current thread of the tenant as not eligible to run just-in-time (JIT) code, wherein the marking indicates that when a method is invoked, a non-JIT version of the method is executed. A processor executes initialization of a first class from an optimization list, wherein the optimization list is a configurable list of classes to be initialized prior to running JIT code. A processor determines that class initialization has been executed for all classes on the optimization list. A processor adjusts the marking to indicate that the current thread is eligible to run JIT code and that the tenant may run JIT code that assumes, without checking, that classes on the optimization list are initialized.Type: ApplicationFiled: September 30, 2016Publication date: January 19, 2017Inventors: Oluwatobi A. Ajila, Graham A. Chapman, Michael H. Dawson, San Hong Li, Hui Shi
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Patent number: 9495185Abstract: In an approach for removing tenant initialization check per tenant for compiled code, a processor receives a request to create a tenant. A processor creates the tenant. A processor marks a current thread of the tenant as not eligible to run just-in-time (JIT) code, wherein the marking indicates that when a method is invoked, a non-JIT version of the method is executed. A processor executes initialization of a first class from an optimization list, wherein the optimization list is a configurable list of classes to be initialized prior to running JIT code. A processor determines that class initialization has been executed for all classes on the optimization list. A processor adjusts the marking to indicate that the current thread is eligible to run JIT code and that the tenant may run JIT code that assumes, without checking, that classes on the optimization list are initialized.Type: GrantFiled: February 23, 2015Date of Patent: November 15, 2016Assignee: International Business Machines CorporationInventors: Oluwatobi A. Ajila, Graham A. Chapman, Michael H. Dawson, San Hong Li, Hui Shi
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Patent number: 9495184Abstract: In an approach for removing tenant initialization check per tenant for compiled code, a processor receives a request to create a tenant. A processor creates the tenant. A processor marks a current thread of the tenant as not eligible to run just-in-time (JIT) code, wherein the marking indicates that when a method is invoked, a non-JIT version of the method is executed. A processor executes initialization of a first class from an optimization list, wherein the optimization list is a configurable list of classes to be initialized prior to running JIT code. A processor determines that class initialization has been executed for all classes on the optimization list. A processor adjusts the marking to indicate that the current thread is eligible to run JIT code and that the tenant may run JIT code that assumes, without checking, that classes on the optimization list are initialized.Type: GrantFiled: September 10, 2015Date of Patent: November 15, 2016Assignee: International Business Machines CorporationInventors: Oluwatobi A. Ajila, Graham A. Chapman, Michael H. Dawson, San Hong Li, Hui Shi
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Publication number: 20160246621Abstract: In an approach for removing tenant initialization check per tenant for compiled code, a processor receives a request to create a tenant. A processor creates the tenant. A processor marks a current thread of the tenant as not eligible to run just-in-time (JIT) code, wherein the marking indicates that when a method is invoked, a non-JIT version of the method is executed. A processor executes initialization of a first class from an optimization list, wherein the optimization list is a configurable list of classes to be initialized prior to running JIT code. A processor determines that class initialization has been executed for all classes on the optimization list. A processor adjusts the marking to indicate that the current thread is eligible to run JIT code and that the tenant may run JIT code that assumes, without checking, that classes on the optimization list are initialized.Type: ApplicationFiled: September 10, 2015Publication date: August 25, 2016Inventors: Oluwatobi A. Ajila, Graham A. Chapman, Michael H. Dawson, San Hong Li, Hui Shi