Patents by Inventor Orin W. Holland

Orin W. Holland has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9196497
    Abstract: An apparatus and method for hydrogenating a sample, such as a semiconductor wafer. The invention utilizes a top electrode comprising a UV-transparent dielectric and a metal contact to provide an electric field to the sample while the sample is irradiated with UV light and hydrogenated with a hydrogenating gas or gasses. The field may be applied to the sample at a number of different pressures, temperatures and concentrations of gas to manipulate the rate and type of hydrogenation. Further, the method of hydrogenating the sample may be used in conjunction with masking and etching techniques.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: November 24, 2015
    Assignee: Amethyst Research, Inc.
    Inventors: Orin W. Holland, Ryan J. Cottier, Terry D. Golding, Khalid Hossain, Ronald Paul Hellmer
  • Publication number: 20120009769
    Abstract: The invention is directed to ion implantation. Ion implantation is a process whereby energetic ions are used to uniformly irradiate the surface of a material—typically a semiconductor wafer. Either atomic or molecular ions are created in an ion source and then extracted for analysis (e.g. by magnetic separation) to ensure the purity of the ion beam. Post-analysis acceleration and scanning of the beam is done prior to sample irradiation. Each dopant-type acts, in general, to increase the conductivity of the silicon.
    Type: Application
    Filed: July 6, 2011
    Publication date: January 12, 2012
    Applicant: Amethyst Research, Inc.
    Inventors: Orin W. Holland, Khalid Hossain
  • Publication number: 20110297534
    Abstract: An apparatus and method for hydrogenating a sample, such as a semiconductor wafer. The invention utilizes a top electrode comprising a UV-transparent dielectric and a metal contact to provide an electric field to the sample while the sample is irradiated with UV light and hydrogenated with a hydrogenating gas or gasses. The field may be applied to the sample at a number of different pressures, temperatures and concentrations of gas to manipulate the rate and type of hydrogenation. Further, the method of hydrogenating the sample may be used in conjunction with masking and etching techniques.
    Type: Application
    Filed: June 8, 2011
    Publication date: December 8, 2011
    Applicant: Amethyst Research, Inc.
    Inventors: Orin W. Holland, Ryan J. Cottier, Terry D. Golding, Khalid Hossain, Ronald Paul Hellmer
  • Publication number: 20100327276
    Abstract: Apparatus and method to improve the operating parameters of HgCdTe-based optoelectric devices by the addition of hydrogen to passivate dislocation defects. A chamber and a UV light source are provided. The UV light source is configured to provide UV radiation within the chamber. The optoelectric device, which may comprise a HgCdTe semiconductor, is placed into the chamber and may be held in position by a sample holder. Hydrogen gas is introduced into the chamber. The material is irradiated within the chamber by the UV light source with the device and hydrogen gas present within the chamber to cause absorption of the hydrogen into the material.
    Type: Application
    Filed: July 7, 2010
    Publication date: December 30, 2010
    Applicant: Amethyst Research, Inc
    Inventors: Orin W. Holland, Terry D. Golding, John H. Dinan, Ronald Paul Hellmer
  • Publication number: 20090309623
    Abstract: A method is provided for measuring defects in semiconductor materials. In one embodiment the method includes placing deuterium in the material and directing an ion beam onto the material to cause a nuclear reaction with the deuterium. Products of the nuclear reaction are analyzed (NRA) to measure the concentration of defects. In other embodiments, a spectroscopic technique is used to detect the deuterium taggant. Lattice defect or total defect occurrences can be selected by selecting the method of placing deuterium in the sample. Defect concentration vs. depth below the surface of material can be determined by varying the energy of the ion beam or by measuring energy profiles of products of the nuclear reaction. The method may be applied to wafers, pixels or other forms of semiconductor materials and may be combined with X-ray analysis of elements on the material.
    Type: Application
    Filed: June 11, 2008
    Publication date: December 17, 2009
    Applicant: Amethyst Research, Inc.
    Inventors: Orin W. Holland, Terry D. Golding, Ronald P. Hellmer, Thomas H. Myers
  • Patent number: 4928156
    Abstract: Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped drains (LDDs) and double diffused drains (DDDs) gives a better profile of the drain region with a reduced junction depth than that obtainable with phosphorus or particularly phosphorus and arsenic together. Good grading of the drain junction to avoid hot carrier instability or hot carrier injection problems is obtained along with shallow source junctions, which minimizes lateral dopant diffusion and decreases the distance between n.sup.- and n.sup.+ regions in GSDs and LDDs.
    Type: Grant
    Filed: March 6, 1989
    Date of Patent: May 22, 1990
    Assignee: Motorola, Inc.
    Inventors: John R. Alvis, James R. Pfiester, Orin W. Holland
  • Patent number: 4920076
    Abstract: A method for enhancing the conversion of Si to SiO.sub.2 in a directional fashion wherein steam or wet oxidation of Si is enhanced by the prior implantation of Ge into the Si. The unique advantages of the Ge impurity include the directional enhancement of oxidation and the reduction in thermal budget, while at the same time, Ge is an electrically inactive impurity.
    Type: Grant
    Filed: April 15, 1988
    Date of Patent: April 24, 1990
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: Orin W. Holland, Dariush Fathy, Clark W. White
  • Patent number: 4908334
    Abstract: Metallic silicide films are formed on silicon substrates by contacting the substrates with a low-energy ion beam of metal ions while moderately heating the substrate. The heating of the substrate provides for the diffusion of silicon atoms through the film as it is being formed to the surface of the film for interaction with the metal ions as they contact the diffused silicon. The metallic silicide films provided by the present invention are contaminant free, of uniform stoichiometry, large grain size, and exhibit low resistivity values which are of particular usefulness for integrated circuit production.
    Type: Grant
    Filed: January 24, 1989
    Date of Patent: March 13, 1990
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: Raymond A. Zuhr, Orin W. Holland
  • Patent number: 4837173
    Abstract: Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped drains (LDDs) and double diffused drains (DDDs) gives a better profile of the drain region with a reduced junction depth than that obtainable with phosphorus or particularly phosphorus and arsenic together. Good grading of the drain junction to avoid hot carrier instability or hot carrier injection problems is obtained along with shallow source junctions, which minimizes lateral dopant diffusion and decreases the distance between n- and n+ regions in GSDs and LDDs.
    Type: Grant
    Filed: July 13, 1987
    Date of Patent: June 6, 1989
    Assignee: Motorola, Inc.
    Inventors: John R. Alvis, James R. Pfiester, Orin W. Holland
  • Patent number: 4748134
    Abstract: An improved process is disclosed for forming the field oxide which provides isolation between adjacent devices in an integrated circuit. In one embodiment of the invention the improvement includes implanting halogen ions, and preferably chlorine ions, into the selected regions of a semiconductor substrate where field oxide is to be formed. The halogen ions are implanted before the field oxide is thermally grown and result in a localized enhancement of the oxide growth rate in the vertical direction compared to the lateral direction. For a given oxidation cycle, the halogen implant results in the growth of a thicker oxide with minimum lateral encroachment.
    Type: Grant
    Filed: May 26, 1987
    Date of Patent: May 31, 1988
    Assignee: Motorola, Inc.
    Inventors: Orin W. Holland, John R. Alvis
  • Patent number: 4743563
    Abstract: A process is disclosed for controlling the surface doping of two regions of a semiconductor device and more specifically for using such control to achieve the necessary field doping in a CMOS device structure. In accordance with one embodiment of the invention a silicon substrate is provided which has first and second regions of opposite conductivity type. A uniform doping such as by ion implantation is provided into each of the conductivity regions. The two regions or portions thereof are then simultaneously differently oxidized to cause a differential segregation of the dopant into the thermally grown oxide. The differential oxide growth can be achieved by selectively implanting halogen ions into the wafer surface prior to the thermal oxidation.
    Type: Grant
    Filed: May 26, 1987
    Date of Patent: May 10, 1988
    Assignee: Motorola, Inc.
    Inventors: James R. Pfiester, John R. Alvis, Orin W. Holland
  • Patent number: 4728619
    Abstract: A complementary metal-oxide-semiconductor (CMOS) isolation structure where the field isolation structure between the adjacent areas of different conductivity types has a channel stop doped with boron or phosphorus affected by germanium. The dual use of germanium and a second dopant selected from the group of phosphorus and boron provides a more precisely placed channel stop, since the germanium retards the diffusion of the boron and phosphorus and surprisingly provides improved width effect for the devices in the well where the channel stop is employed. Alternatively, the germanium may be placed in such a manner as to avoid retarding absorption of boron or phosphorus into the field oxide and retard its diffusion over the well of a different conductivity type where it is not desired.
    Type: Grant
    Filed: June 19, 1987
    Date of Patent: March 1, 1988
    Assignee: Motorola, Inc.
    Inventors: James R. Pfiester, John R. Alvis, Orin W. Holland
  • Patent number: 4704367
    Abstract: A technique for suppressing hillock growth in metal films on integrated circuits through multiple thermal cycles by argon implantation. Although it was known that ion implantation of many species such as arsenic suppressed the growth of hillocks in metal films through one thermal cycle, it was discovered that only one of the proposed ions, argon, would suppress hillock formation for multiple subsequent thermal cycles. For the other species, hillock formation would reoccur after multiple cycles. This characteristic is important for double layer metal (DLM) processes to prevent interlayer shorting.
    Type: Grant
    Filed: April 21, 1986
    Date of Patent: November 3, 1987
    Inventors: John R. Alvis, Orin W. Holland