Patents by Inventor Orna Etzion

Orna Etzion has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7624384
    Abstract: Embodiments of the invention disclose a method, apparatus and system of translating a source binary code into a target binary code. The translation according to embodiments of the invention may include determining whether or not a previously translated code block that relates to a source fragment to be currently translated may be reused for execution by a target processor. A reusability status of the previously translated code block may be determined based on a reusability status of a group of previously translated code blocks. In some embodiments, when no previously translated code blocks relating to the currently translated source fragment are found, the source fragment may be translated into a new target code block, which may be executed by the target processor. The new target code block may then be added to a group of previously translated code blocks.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: November 24, 2009
    Assignee: Intel Corporation
    Inventors: Peng Zhang, Jianhui Li, Alex Skaletsky, Orna Etzion
  • Patent number: 7493599
    Abstract: Device, system and method for detection and handling of misaligned data access. A method may include, for example, detecting misaligned data access resulting from execution of a code block translated from a first format suitable for a first computing platform to a second format suitable for a second computing platform, and modifying said code block according to said misaligned data access.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: February 17, 2009
    Assignee: Intel Corporation
    Inventors: Harold Theodore Devor, Orna Etzion, Jian Ping Chen
  • Patent number: 7380240
    Abstract: A binary translation module is to translate a first sequence of instructions associated with a source architecture into a second sequence of instructions associated with a target architecture. The first sequence includes one or more floating point control instructions and the second sequence does not include a floating point control instruction. Results produced by executing the second sequence on a processor that complies with the target architecture are substantially the same as results produced by executing the first sequence on a processor that complies with the source architecture.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: May 27, 2008
    Assignee: Intel Corporation
    Inventors: Qi Zhang, Jianhui Li, Orna Etzion
  • Patent number: 7363471
    Abstract: A method may translate a set of source instructions into a set of target instructions, execute the set of target instructions, and unmask a denormal input control bit if the set of source instructions uses a denormal input handling mechanism. A method may detect at least one denormal exception of a faulty target instruction by executing the set of target instructions; assign a predetermined value to one or more denormal operands of the faulty target instruction; and execute the faulty target instruction with the predetermined value for the one or more denormal operands. An apparatus, system, and machine-readable medium may perform such methods.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: April 22, 2008
    Assignee: Intel Corporation
    Inventors: Sion Berkowits, Orna Etzion, Li Jianhui
  • Patent number: 7340592
    Abstract: A method of generating an expected TOS during translation of instructions. The method includes translating a first block of instructions executable in a first processor architecture, into a translated first block of instructions executable in a second processor architecture, wherein the translated first block of instructions operate with a stack of data entry positions. During the translation, an expected Top of Stack (TOS) position in the stack for the first block of code is generated.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: March 4, 2008
    Assignee: Intel Corporation
    Inventor: Orna Etzion
  • Patent number: 7249350
    Abstract: An arrangement is provided for translating a plurality of scalar single instruction multiple data stream (SIMD) instructions into a plurality of optimized non-scalar SIMD instructions to be executed on a target architecture supporting only parallel SIMID instructions. After receiving a plurality of scalar SIiVLD instructions, translation from the scalar SIMD instructions to non-scalar SIMD instructions is performed. The translation is optimized so that the number of translated non-scalar SIMD instructions is minimized. The translated non-scalar SIIViD instructions are executed on a target architecture that supports only parallel SIMD instructions.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: July 24, 2007
    Assignee: Intel Corporation
    Inventors: Yun Wang, Orna Etzion
  • Patent number: 7219336
    Abstract: In one embodiment of the invention, a register format of a source register operated on by a source instruction in a source block of code is determined. The register format includes an input instruction format and an output block format of the source block of code. The source block of code runs in a source architecture. The source register has multiple formats and is used as an input of the source instruction. The input instruction format contains format of the source register expected by the source instruction. The output block format contains format of the source register after the source block of code is executed. An instruction format inconsistency is detected between the source register and a target register of a target architecture during a translation phase of a binary translation that translates the source block of code into a target block of code running in the target architecture.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: May 15, 2007
    Assignee: Intel Corporation
    Inventors: Jianhui Li, Bo Huang, Orna Etzion
  • Patent number: 7219335
    Abstract: A method of monitoring processor resources. To monitor a processor resource, first a set of needed resources is determined at the beginning of a block of code. A test is then performed to determine if the set of needed resources is available at the start of the block of code. An error is signaled if the needed resources are not available at the beginning of the block of code.
    Type: Grant
    Filed: December 8, 1999
    Date of Patent: May 15, 2007
    Assignee: Intel Corporation
    Inventors: Gal Moas, Orna Etzion
  • Publication number: 20060294508
    Abstract: One embodiment of the invention provides a method to translate a set of source instructions into a set of target instructions, to execute the set of target instructions, and to unmask a denormal input control bit if the set of source instructions uses a denormal input handling mechanism. Another embodiment of the invention provide a method to detect at least one denormal exception of a faulty target instruction by executing the set of target instructions; to assign a predetermined value to one or more denormal operands of the faulty target instruction; and to execute the faulty target instruction with the predetermined value for the one or more denormal operands. Embodiments of the invention also provide apparatus, system, and machine-readable medium thereof.
    Type: Application
    Filed: June 27, 2005
    Publication date: December 28, 2006
    Inventors: Sion Berkowits, Orna Etzion, Jianhui Li
  • Publication number: 20060114132
    Abstract: Embodiments of the invention disclose a method, apparatus and system of translating a source binary code into a target binary code. The translation according to embodiments of the invention may include determining whether or not a previously translated code block that relates to a source fragment to be currently translated may be reused for execution by a target processor. A reusability status of the previously translated code block may be determined based on a reusability status of a group of previously translated code blocks. In some embodiments, when no previously translated code blocks relating to the currently translated source fragment are found, the source fragment may be translated into a new target code block, which may be executed by the target processor. The new target code block may then be added to a group of previously translated code blocks.
    Type: Application
    Filed: November 30, 2004
    Publication date: June 1, 2006
    Inventors: Peng Zhang, Jianhui Li, Alex Skaletsky, Orna Etzion
  • Publication number: 20060095896
    Abstract: A set of source instructions that complies with a source architecture is dynamically translated into a set of target instructions that complies with a target architecture. At least some of exception-related dependencies between faulty instructions and their immediate preceding instructions, in the translated target instruction binary code, are removed. Instead, dependencies between mapping registers and their representative registers that are associated with the faulty instructions are created. Computations of the values of mapping registers, for the recovery of canonical registers, are delayed until exceptions are actually detected during execution of the target instructions. The restoration of context of source instructions at the exception-related recovery points is realized through the invoking of associated recovery functions.
    Type: Application
    Filed: September 28, 2004
    Publication date: May 4, 2006
    Inventors: Jianhui Li, Orna Etzion
  • Patent number: 7000226
    Abstract: Mapping of exception masks between source and target architectures with different numbers of exception masks enables a binary translator to translate code from the source to the target architecture and to determine an appropriate state for the source architecture if an exception is raised when executing the translated code.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: February 14, 2006
    Assignee: Intel Corporation
    Inventors: Baiming Gao, Yun Wang, Yigal Zemach, Orna Etzion, Jianhui Li
  • Publication number: 20050149915
    Abstract: Methods and apparatus for optimizing a program undergoing dynamic binary translation using profile information are disclosed. A disclosed system optimizes foreign program instructions through an enhanced dynamic binary translation process. The foreign program instructions are translated into native program instructions. Loops within the native program instructions are instrumented with profiling instructions and optimized. The profiling information is collected during execution of the loop. After profiling information is collected, the loop may be further optimized by inserting prefetching instructions into the optimized loop. The prefetched loop is then linked back into the native program instructions and is executable.
    Type: Application
    Filed: December 29, 2003
    Publication date: July 7, 2005
    Inventors: Youfeng Wu, Orna Etzion
  • Publication number: 20050149913
    Abstract: A source binary code that complies with a source architecture is translated to a target binary code that complies with a target architecture. The target binary code includes a first target portion translated from a respective source portion of the source binary code. During execution of the target binary code on a processor that complies with a target architecture, it is determined whether to retranslate the source portion to produce a second target portion that is more optimized to the target architecture than the first target portion or to retranslate the source portion to produce a third target portion that is more optimized to the target architecture than the second target portion.
    Type: Application
    Filed: December 29, 2003
    Publication date: July 7, 2005
    Inventors: Yun Wang, Orna Etzion
  • Publication number: 20050138608
    Abstract: A binary translation module is to translate a first sequence of instructions associated with a source architecture into a second sequence of instructions associated with a target architecture. The first sequence includes one or more floating point control instructions and the second sequence does not include a floating point control instruction. Results produced by executing the second sequence on a processor that complies with the target architecture are substantially the same as results produced by executing the first sequence on a processor that complies with the source architecture.
    Type: Application
    Filed: December 23, 2003
    Publication date: June 23, 2005
    Inventors: Qi Zhang, Jianhui Li, Orna Etzion
  • Publication number: 20050114845
    Abstract: Device, system and method for detection and handling of misaligned data access. A method may include, for example, detecting misaligned data access resulting from execution of a code block translated from a first format suitable for a first computing platform to a second format suitable for a second computing platform, and modifying said code block according to said misaligned data access.
    Type: Application
    Filed: November 26, 2003
    Publication date: May 26, 2005
    Inventors: Harold Devor, Orna Etzion, Jian Chen
  • Publication number: 20040064810
    Abstract: An arrangement is provided for translating a plurality of scalar single instruction multiple data stream (SIMD) instructions into a plurality of optimized non-scalar SIMD instructions to be executed on a target architecture supporting only parallel SIMD instructions. After receiving a plurality of scalar SIMD instructions, translation from the scalar SIMD instructions to non-scalar SIMD instructions is performed. The translation is optimized so that the number of translated non-scalar SIMD instructions is minimized. The translated non-scalar SIMD instructions are executed on a target architecture that supports only parallel SIMD instructions.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 1, 2004
    Inventors: Yun Wang, Orna Etzion
  • Publication number: 20030154419
    Abstract: In one embodiment of the invention, a first last use of a first canonical register in a block of code is recorded after a renaming. The first canonical register is mapped to a first original register. One of a first rollback and a first recovery is applied to the first original register based on whether the recorded first last use occurs before a first last definition of the first original register in the block of code.
    Type: Application
    Filed: January 10, 2002
    Publication date: August 14, 2003
    Inventors: Binyu Zang, Yun Wang, Orna Etzion
  • Publication number: 20030140335
    Abstract: In one embodiment of the invention, a register format of a source register operated on by a source instruction in a source block of code is determined. The register format includes an input instruction format and an output block format of the source block of code. The source block of code runs in a source architecture. The source register has multiple formats and is used as an input of the source instruction. The input instruction format contains format of the source register expected by the source instruction. The output block format contains format of the source register after the source block of code is executed. An instruction format inconsistency is detected between the source register and a target register of a target architecture during a translation phase of a binary translation that translates the source block of code into a target block of code running in the target architecture.
    Type: Application
    Filed: January 3, 2002
    Publication date: July 24, 2003
    Inventors: Jianhui Li, Bo Huang, Orna Etzion
  • Publication number: 20030126419
    Abstract: Mapping of exception masks between source and target architectures with different numbers of exception masks enables a binary translator to translate code from the source to the target architecture and to determine an appropriate state for the source architecture if an exception is raised when executing the translated code.
    Type: Application
    Filed: January 2, 2002
    Publication date: July 3, 2003
    Inventors: Baiming Gao, Yun Wang, Yigal Zemach, Orna Etzion, Jianhui Li