Patents by Inventor Owen R. Fay

Owen R. Fay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11574820
    Abstract: Methods for manufacturing semiconductor devices having a flexible reinforcement structure, and associated systems and devices, are disclosed herein. In one embodiment, a method of manufacturing a semiconductor device includes electrically coupling at least one semiconductor die to a redistribution structure on a first carrier. The semiconductor die can include a first surface connected to the redistribution structure and a second surface spaced apart from the redistribution structure. The method also includes reducing a thickness of the semiconductor die to no more than 10 ?m. The method further includes coupling a flexible reinforcement structure to the second surface of the at least one semiconductor die.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: February 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Chan H. Yoo
  • Publication number: 20230025886
    Abstract: Semiconductor device package assemblies and associated methods are disclosed herein. The semiconductor device package assembly includes (1) a base component having a front side and a back side, the base component having a first metallization structure at the front side; (2) a semiconductor device package having a first side, a second side with a recess, and a second metallization structure at the first side and a contacting region exposed in the recess at the second side; (3) an interconnect structure at least partially positioned in the recess at the second side of the semiconductor device package; and (4) a thermoset material or structure between the front side of the base component and the second side of the semiconductor device package. The interconnect structure is in the thermoset material and includes discrete conductive particles electrically coupled to one another.
    Type: Application
    Filed: October 3, 2022
    Publication date: January 26, 2023
    Inventors: Owen R. Fay, Chan H. Yoo
  • Publication number: 20230008292
    Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.
    Type: Application
    Filed: September 15, 2022
    Publication date: January 12, 2023
    Inventors: Randon K. Richards, Aparna U. Limaye, Owen R. Fay, Dong Soon Lim
  • Patent number: 11552045
    Abstract: Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly comprises a die stack including a plurality of semiconductor dies, and a routing substrate mounted on the die stack. The routing substrate includes an upper surface having a redistribution structure. The semiconductor assembly also includes a plurality of electrical connectors coupling the redistribution structure to at least some of the semiconductor dies. The semiconductor assembly further includes a controller die mounted on the routing substrate. The controller die includes an active surface that faces the upper surface of the routing substrate and is electrically coupled to the redistribution structure, such that the routing substrate and the semiconductor dies are electrically coupled to the controller die via the redistribution structure.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: January 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Madison E. Wale, James L. Voelz, Dylan W. Southern, Dustin L. Holloway
  • Publication number: 20230005904
    Abstract: An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.
    Type: Application
    Filed: September 12, 2022
    Publication date: January 5, 2023
    Inventors: Owen R. Fay, Chan H. Yoo
  • Publication number: 20220375917
    Abstract: A semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. The substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. The substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes applying CMOS processing to a silicon substrate, forming back end of line (BEOL) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the BEOL layers, and forming a redistribution layer on the second side of the substrate.
    Type: Application
    Filed: August 4, 2022
    Publication date: November 24, 2022
    Inventors: Chan H. Yoo, Owen R. Fay
  • Publication number: 20220375902
    Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.
    Type: Application
    Filed: August 5, 2022
    Publication date: November 24, 2022
    Inventors: Owen R. Fay, Randon K. Richards, Aparna U. Limaye, Dong Soon Lim, Chan H. Yoo, Bret K. Street, Eiichi Nakano, Shijian Luo
  • Patent number: 11482504
    Abstract: Systems and methods for a semiconductor device having an edge-notched substrate are provided. The device generally includes a substrate having a front side, a backside having substrate contacts, and an inward notch at an edge of the substrate. The device includes a die having an active side attached to the front side of the substrate and positioned such that bond pads of the die are accessible from the backside of the substrate through the inward notch. The device includes wire bonds routed through the inward notch and electrically coupling the bond pads of the die to the substrate contacts. The device may further include a second die having an active side attached to the backside of the first die and positioned laterally offset from the first die such that the second bond pads are accessible by wire bonds around the edge of the first die and through the inward notch.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: October 25, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Madison E. Wale, James L. Voelz, Dylan W. Southern
  • Patent number: 11476241
    Abstract: An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: October 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, Owen R. Fay
  • Patent number: 11462472
    Abstract: Semiconductor device package assemblies and associated methods are disclosed herein. The semiconductor device package assembly includes (1) a base component having a front side and a back side, the base component having a first metallization structure at the front side; (2) a semiconductor device package having a first side, a second side with a recess, and a second metallization structure at the first side and a contacting region exposed in the recess at the second side; (3) an interconnect structure at least partially positioned in the recess at the second side of the semiconductor device package; and (4) a thermoset material or structure between the front side of the base component and the second side of the semiconductor device package. The interconnect structure is in the thermoset material and includes discrete conductive particles electrically coupled to one another.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: October 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Chan H. Yoo
  • Patent number: 11456284
    Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: September 27, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Randon K. Richards, Aparna U. Limaye, Owen R. Fay, Dong Soon Lim
  • Publication number: 20220302090
    Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more stacks of microelectronic devices are located on the substrate, and microelectronic devices of the stacks are connected to vertical conductive paths external to the stacks and extending to the substrate and to lateral conductive paths extending between the stacks. Methods of fabrication are also disclosed.
    Type: Application
    Filed: June 7, 2022
    Publication date: September 22, 2022
    Inventors: Aparna U. Limaye, Dong Soon Lim, Randon K. Richards, Owen R. Fay
  • Publication number: 20220293569
    Abstract: Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.
    Type: Application
    Filed: June 3, 2022
    Publication date: September 15, 2022
    Inventor: Owen R. Fay
  • Publication number: 20220293506
    Abstract: Package-on-package systems for packaging semiconductor devices. In one embodiment, a package-on-package system comprises a first semiconductor package device and a second semiconductor package device. The first package device includes a base substrate including a first side having a die-attach region and a peripheral region, a first semiconductor die attached to the base substrate at the die-attach region, wherein the first semiconductor die has a front side facing the first side of the base substrate and a backside spaced apart from the first side of the base substrate by a first distance, and a high density interconnect array in the perimeter region of the base substrate outside of the die-attach region. The interconnect array has a plurality of interconnects that extend from the first side of the base substrate by a second distance greater than the first distance. The second semiconductor device package is electrically coupled corresponding individual interconnects.
    Type: Application
    Filed: June 1, 2022
    Publication date: September 15, 2022
    Inventors: Owen R. Fay, Jack E. Murray
  • Patent number: 11444067
    Abstract: An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Chan H. Yoo
  • Patent number: 11410981
    Abstract: A semiconductor device assembly that includes first and second semiconductor devices connected directly to a first side of a substrate and a plurality of interconnects connected to a second side of the substrate. The substrate is configured to enable the first and second semiconductor devices to communicate with each other through the substrate. The substrate may be a silicon substrate that includes complementary metal-oxide-semiconductor (CMOS) circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes applying CMOS processing to a silicon substrate, forming back end of line (BEOL) layers on a first side of the substrate, attaching a memory device and a processing unit directly to the BEOL layers, and forming a redistribution layer on the second side of the substrate.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Chan H. Yoo, Owen R. Fay
  • Patent number: 11410973
    Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Randon K. Richards, Aparna U. Limaye, Dong Soon Lim, Chan H. Yoo, Bret K. Street, Eiichi Nakano, Shijian Luo
  • Patent number: 11398465
    Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: July 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Rich Fogal, Owen R. Fay
  • Patent number: 11393791
    Abstract: Semiconductor device package assemblies and associated methods are disclosed herein. In some embodiments, the semiconductor device package assembly includes (1) a base component having a front side and a back side opposite the first side, the base component having a first metallization structure at the front side, the first metallization structure being exposed in a contacting area at the front side; (2) a semiconductor device package having a first side and a second side, the semiconductor device package having a second metallization structure at the first side; and (3) a metal bump at least partially positioned in the recess and electrically coupled to the second metallization structure and the first metallization structure.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Owen R. Fay
  • Patent number: 11393794
    Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, at least one surface mount component operably coupled to conductive traces of at least one dielectric material, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Randon K. Richards, Owen R. Fay, Aparna U. Limaye, Dong Soon Lim