Patents by Inventor Owen Y. Loh

Owen Y. Loh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10978568
    Abstract: Techniques are disclosed for passivation of transistor channel region interfaces. In some cases, the transistor channel region interfaces to be passivated include the interface between the semiconductor channel and the gate dielectric and/or the interface between the sub-channel semiconductor material and isolation material. For example, an aluminum oxide (also referred to as alumina) layer may be used to passivate channel/gate interfaces where the channel material includes silicon germanium, germanium, or a III-V material. The techniques can be used to reduce the interface trap density at the channel/gate interface and the techniques can also be used to passivate the channel/gate interface in both gate first and gate last process flows. The techniques may also include an additional passivation layer at the sub-channel/isolation interface to, for example, avoid incurring additional parasitic capacitance penalty.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 13, 2021
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Mark R. Brazier, Anand S. Murthy, Tahir Ghani, Owen Y. Loh
  • Publication number: 20200286686
    Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.
    Type: Application
    Filed: March 7, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sou-Chi Chang, Ashish Verma Penumatcha, Nazila Haratipour, Seung Hoon Sung, Owen Y. Loh, Jack Kavalieros, Uygar E. Avci, Ian A. Young
  • Publication number: 20200286685
    Abstract: Described is a ferroelectric based capacitor that reduces non-polar monoclinic phase and increases polar orthorhombic phase by epitaxial strain engineering in the oxide thin film and/or electrodes. As such, both memory window and reliability are improved. The capacitor comprises: a first structure comprising metal, wherein the first structure has a first lattice constant; a second structure comprising metal, wherein the second structure has a second lattice constant; and a third structure comprising ferroelectric material (e.g., oxide of Hf or Zr), wherein the third structure is between and adjacent to the first and second structures, wherein the third structure has a third lattice constant, and wherein the first and second lattice constants are smaller than the third lattice constant.
    Type: Application
    Filed: March 6, 2019
    Publication date: September 10, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Ching Lin, Sou-Chi Chang, Ashish Verma Penumatcha, Nazila Haratipour, Seung Hoon Sung, Owen Y. Loh, Jack Kavalieros, Uygar E. Avci, Ian A. Young
  • Publication number: 20180248015
    Abstract: Techniques are disclosed for passivation of transistor channel region interfaces. In some cases, the transistor channel region interfaces to be passivated include the interface between the semiconductor channel and the gate dielectric and/or the interface between the sub-channel semiconductor material and isolation material. For example, an aluminum oxide (also referred to as alumina) layer may be used to passivate channel/gate interfaces where the channel material includes silicon germanium, germanium, or a III-V material. The techniques can be used to reduce the interface trap density at the channel/gate interface and the techniques can also be used to passivate the channel/gate interface in both gate first and gate last process flows. The techniques may also include an additional passivation layer at the sub-channel/isolation interface to, for example, avoid incurring additional parasitic capacitance penalty.
    Type: Application
    Filed: September 25, 2015
    Publication date: August 30, 2018
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, MARK R. BRAZIER, ANAND S. MURTHY, TAHIR GHANI, OWEN Y. LOH
  • Publication number: 20110317325
    Abstract: The present invention provides for replacement of conventionally-used metal electrodes in NEMS devices with electrodes that include non-metallic materials comprised of diamond-like carbon or a dielectric coated metallic film having greater electrical contact resistance and lower adhesion with a contacting nanostructure. This reduces Joule heating and stiction, improving device reliability.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 29, 2011
    Inventors: Horacio D. Espinosa, Owen Y. Loh, Xiaoding Wei