Patents by Inventor Padam Jain

Padam Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210366807
    Abstract: Systems and methods for utilizing the dead space around the periphery of a chip for sealing a direct liquid cooled module are disclosed. One of the functions of a direct liquid cooled module is to provide cooling liquid to components located on a chip. A groove member for receiving a sealing member may be applied to the top surface of the chip. The groove member may be directly deposited to the top surface or coupled thereto via an adhesive and/or epoxy. The groove member may be in the form of opposing sidewalls or a u-shaped structure each of which form a partial enclosure for receipt of the sealing member. The groove member may be located entirely within the dead space or at least partially within the dead space and partially within a central area in which the chip components are located. The sealing member may be an O-ring or a gasket.
    Type: Application
    Filed: May 21, 2020
    Publication date: November 25, 2021
    Inventors: Jorge Padilla, Madhusudan K. Iyengar, Connor Burgess, Padam Jain, Yuan Li, Feini Zhang
  • Publication number: 20210366806
    Abstract: Systems and methods for using spring force based compliance to minimize the bypass liquid flow gaps between the tops of chip microfins and bottom side of manifold ports are disclosed herein. A fluid delivery and exhaust manifold structure provides direct liquid cooling of a module. The manifold sits on top of a chip with flow channels. Inlet and outlet channels of the manifold in contact with flow channels of the chip creates an intricate crossflow path for the coolant resulting in improved heat transfer between the chip and the working fluid. The module is also designed with pressure reduction features using internal leakage flow openings to account for pressure differential between fluid entering and being expelled from the module.
    Type: Application
    Filed: May 20, 2020
    Publication date: November 25, 2021
    Inventors: Madhusudan K. Iyengar, Connor Burgess, Emad Samadiani, Padam Jain, Jorge Padilla, Feini Zhang, Yuan Li
  • Publication number: 20210366841
    Abstract: A weight optimized stiffener for use in a semiconductor device is disclosed herein. In one example, the stiffener is made of AlSiC for its weight and thermal properties. An O-ring provides sealing between a top surface of the stiffener and a component of the semiconductor device and adhesive provides sealing between a bottom surface of the stiffener and another component of the semiconductor device. The stiffener provides warpage control for a lidless package while enabling direct liquid cooling of a chip or substrate.
    Type: Application
    Filed: May 19, 2020
    Publication date: November 25, 2021
    Inventors: Madhusudan K. Iyengar, Connor Burgess, Padam Jain, Emad Samadiani, Yuan Li
  • Patent number: 10964625
    Abstract: A device for direct liquid cooling is disclosed. The device includes a packaged assembly disposed on a substrate. The device also includes a metal channel layer having a plurality of channels disposed on top of the packaged assembly, and a top seal disposed on the metal channel layer. The top seal has at least one inlet and at least one outlet for direct liquid cooling. The metal channel layer includes copper or silver. The packaged assembly can also include silicon channels. In addition, the method of producing the device is also disclosed.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: March 30, 2021
    Assignee: Google LLC
    Inventors: Padam Jain, Yuan Li, Teckgyu Kang, Madhusudan Iyengar
  • Publication number: 20200273777
    Abstract: A device for direct liquid cooling is disclosed. The device includes a packaged assembly disposed on a substrate. The device also includes a metal channel layer having a plurality of channels disposed on top of the packaged assembly, and a top seal disposed on the metal channel layer. The top seal has at least one inlet and at least one outlet for direct liquid cooling. The metal channel layer includes copper or silver. The packaged assembly can also include silicon channels. In addition, the method of producing the device is also disclosed.
    Type: Application
    Filed: February 26, 2019
    Publication date: August 27, 2020
    Inventors: Padam Jain, Yuan Li, Teckgyu Kang, Madhusudan Iyengar
  • Patent number: 10156254
    Abstract: The present disclosure relates to the field of mechanical engineering. The bearing of the present disclosure comprises few components and can be assembled easily on site. The bearing includes a housing and a plurality of sectional elements. The housing is disposed on a base and has a hollow profile. The plurality of sectional elements is disposed within the housing and is configured to hold the component therewithin. The plurality of sectional elements facilitates rotation of the component. Each of the plurality of sectional elements is defined by an operative outer surface and an operative inner surface. The operative outer surface has a shape complementary to an operative inner surface of the housing. The operative inner surface of each of the plurality of sectional elements has a shape complementary to the component to be held within the bearing.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: December 18, 2018
    Assignee: MAHINDRA SUSTEN PVT LTD.
    Inventors: Sandeep Jayawant Bhosale, Apurav Padam Jain, Basant Kumar Jain
  • Patent number: 9832865
    Abstract: A build-up process for fabricating a multi-layer PCB is provided during which a mezzanine redistribution, or routing, structure is formed within one of the PCB dielectric material layers that allows additional electrical interconnections (i.e., traces and crossovers) to be made within that layer, thereby obviating the need to add an additional PCB layer in order to make those interconnections. The mezzanine redistribution structure also can be interconnected with the metal layers that are above and below it to further increase routing complexity and flexibility. The mezzanine redistribution structure can be formed without increasing the total thickness of the PCB and without substantially increasing costs.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: November 28, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Jack Ajoian, Padam Jain
  • Publication number: 20170311444
    Abstract: A build-up process for fabricating a multi-layer PCB is provided during which a mezzanine redistribution, or routing, structure is formed within one of the PCB dielectric material layers that allows additional electrical interconnections (i.e., traces and crossovers) to be made within that layer, thereby obviating the need to add an additional PCB layer in order to make those interconnections. The mezzanine redistribution structure also can be interconnected with the metal layers that are above and below it to further increase routing complexity and flexibility. The mezzanine redistribution structure can be formed without increasing the total thickness of the PCB and without substantially increasing costs.
    Type: Application
    Filed: April 26, 2016
    Publication date: October 26, 2017
    Inventors: Jack Ajoian, Padam Jain
  • Patent number: 9788416
    Abstract: Embodiments disclosed include a multilayer substrate for semiconductor packaging. The substrate may include a first layer with a first side with an xy-plane and individual locations on the first side have a first side distance below the first side xy-plane, and a second side with a second side xy-plane and individual locations on the second side may have a second side distance below the second side xy-plane; and a second layer with a first side coupled to the second side of the first layer and a second side opposite the first side of the second layer, wherein a thickness of the second layer at the individual locations on the second layer may be comprised of the first side distance plus the second side distance. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: October 10, 2017
    Assignee: INTEL CORPORATION
    Inventors: Wei-Lun Kane Jen, Padam Jain, Dilan Seneviratne, Chi-Mon Chen
  • Publication number: 20170223839
    Abstract: A method is provided for fabricating an electromagnetic shield for an electronic component on a PCB. The method includes providing a patterned metal layer; laminating the patterned metal layer with a second dielectric layer; forming a cavity in the second dielectric layer; applying a dry film resist over the second dielectric layer and the cavity; stripping the dry film resist from the second dielectric layer and portions of the cavity adjacent the cavity side walls; depositing a seed layer and metal over the second dielectric layer and the dry film resist; etching the preplating layer and the seed layer from top surfaces of a remainder of the dry film resist and the second dielectric layer; and stripping the remainder of the dry film resist, thereby exposing the preplating layer on the side walls of the cavity to provide the electromagnetic shield.
    Type: Application
    Filed: January 28, 2016
    Publication date: August 3, 2017
    Inventors: Padam Jain, Sarah Haney, Ashish Alawani
  • Publication number: 20170215278
    Abstract: A coreless substrate of a printed circuit board is provided. The coreless substrate includes a first outer metal layer; a first primer layer formed on the first outer metal layer; a first layer of functional prepreg material formed on the first primer layer; a second primer layer formed over the first layer of functional prepreg material; and a second outer metal layer formed on the second primer layer. The first outer metal layer corresponds to a first outer most surface of the printed circuit board, and the second outer metal layer corresponds to a second outer most surface of the printed circuit board.
    Type: Application
    Filed: January 27, 2016
    Publication date: July 27, 2017
    Inventors: Padam Jain, Sarah Haney, Lea-Teng Lee
  • Publication number: 20170070187
    Abstract: The present disclosure envisages a solar tracking system. The solar tracking system of the present disclosure relates to the field of solar energy. The solar tracking system of the present disclosure has a simple operation and is self-powered and requires less maintenance. The principal use of the solar tracking system of the present disclosure is in solar power plants.
    Type: Application
    Filed: September 8, 2016
    Publication date: March 9, 2017
    Inventors: Apurav Padam Jain, Basant Kumar Jain, Akshay Keshav Roge, Rohit Gupta
  • Publication number: 20170063292
    Abstract: The present disclosure envisages a solar tracking system for a solar panel. The solar tracking system comprises a bearing, a torque tube and a linear actuator. The bearing is coupled to the solar panel by means of rails, typically, C-channel, hat section rails. The torque tube is connected to the solar panel, wherein the torque tube is configured to be angularly displaced within the bearing. The linear actuator is coupled to the torque tube, wherein the linear actuator is configured to angularly displace the torque tube, thereby displacing the solar panel. The linear actuator includes a worm and worm gear arrangement of a rack and pinion arrangement. The solar tracking system is powered by either an auxiliary solar panel and/or a battery.
    Type: Application
    Filed: August 23, 2016
    Publication date: March 2, 2017
    Inventors: Basant Kumar Jain, Apurav Padam Jain, Sandeep Jayawant Bhosale
  • Publication number: 20170058944
    Abstract: The present disclosure relates to the field of mechanical engineering. The bearing of the present disclosure comprises few components and can be assembled easily on site. The bearing includes a housing and a plurality of sectional elements. The housing is disposed on a base and has a hollow profile. The plurality of sectional elements is disposed within the housing and is configured to hold the component therewithin. The plurality of sectional elements facilitates rotation of the component. Each of the plurality of sectional elements is defined by an operative outer surface and an operative inner surface. The operative outer surface has a shape complementary to an operative inner surface of the housing. The operative inner surface of each of the plurality of sectional elements has a shape complementary to the component to be held within the bearing.
    Type: Application
    Filed: August 23, 2016
    Publication date: March 2, 2017
    Inventors: Sandeep Jayawant BHOSALE, Apurav Padam JAIN, Basant Kumar JAIN
  • Publication number: 20160329274
    Abstract: Embodiments disclosed include a multilayer substrate for semiconductor packaging. The substrate may include a first layer with a first side with an xy-plane and individual locations on the first side have a first side distance below the first side xy-plane, and a second side with a second side xy-plane and individual locations on the second side may have a second side distance below the second side xy-plane; and a second layer with a first side coupled to the second side of the first layer and a second side opposite the first side of the second layer, wherein a thickness of the second layer at the individual locations on the second layer may be comprised of the first side distance plus the second side distance. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 22, 2014
    Publication date: November 10, 2016
    Inventors: Wei-Lun Kane Jen, Padam Jain, Dilan Seneviratne, Chi-Mon Chen