Patents by Inventor Palanivel Rajan Shanmugavelayutham

Palanivel Rajan Shanmugavelayutham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9934380
    Abstract: In an example, there is provided a system and method for execution profiling detection of malicious software objects. An execution profiling (EXP) engine may be provided in conjunction with a binary translation engine (BTE). Both may operate within a trusted execution environment (TEE). Because many malware objects make assumptions about memory usage of host applications, they may cause exceptions when those assumptions prove untrue. The EXP engine may proactively detect such exceptions via the BTE when the BTE performs its translation function. Thus, malicious behavior may be detected before a binary runs on a system, and remedial measures may be provided.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: April 3, 2018
    Assignee: McAfee, LLC
    Inventors: Greg W. Dalcher, Koichi Yamada, Palanivel Rajan Shanmugavelayutham, Jitendra P. Singh
  • Patent number: 9904782
    Abstract: Providing synchronous processing of the designated computing events using hardware-assisted virtualization technology by performing at least the following: detecting a designated computing event using a high priority, low capability routine, creating a copy code in an alternate memory space of a first code located in a first memory space, modifying the copy code to call for analysis of at least a portion of the copy code that corresponds to the first code, switching execution of the first code with the modified copy code using an address translation data structure that translates a guest memory address to a host memory address after a return of the high priority, low capability routine; and analyzing synchronously the at least a portion of the code within the copy code that corresponds to the first code based on the replacement of the first code with the modified copy code.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: February 27, 2018
    Assignee: McAfee, LLC
    Inventors: Carl D. Woodward, Jennifer Mankin, Dmitri Rubakha, Palanivel Rajan Shanmugavelayutham, Vadim Sukhomlinov
  • Publication number: 20170116419
    Abstract: Providing synchronous processing of the designated computing events using hardware-assisted virtualization technology by performing at least the following: detecting a designated computing event using a high priority, low capability routine, creating a copy code in an alternate memory space of a first code located in a first memory space, modifying the copy code to call for analysis of at least a portion of the copy code that corresponds to the first code, switching execution of the first code with the modified copy code using an address translation data structure that translates a guest memory address to a host memory address after a return of the high priority, low capability routine; and analyzing synchronously the at least a portion of the code within the copy code that corresponds to the first code based on the replacement of the first code with the modified copy code.
    Type: Application
    Filed: October 27, 2015
    Publication date: April 27, 2017
    Inventors: Carl D. Woodward, Jennifer Mankin, Dmitri Rubakha, Palanivel Rajan Shanmugavelayutham, Vadim Sukhomlinov
  • Publication number: 20160381043
    Abstract: Particular embodiments described herein provide for an electronic device that can be configured to monitor code as it executes. The code can include self-modifying code. The system can log an event if the self-modifying code occurred in a GetPC address region.
    Type: Application
    Filed: September 26, 2015
    Publication date: December 29, 2016
    Applicant: McAfee, Inc.
    Inventors: Koichi Yamada, Palanivel Rajan Shanmugavelayutham, Greg W. Dalcher, Sravani Konda
  • Patent number: 9405551
    Abstract: In an embodiment, a processor includes a binary translation (BT) container having code to generate a binary translation of a first code segment and to store the binary translation in a translation cache, a host entity logic to manage the BT container and to identify the first code segment, and protection logic to isolate the BT container from a software stack. In this way, the BT container is configured to be transparent to the software stack. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: August 2, 2016
    Assignee: Intel Corporation
    Inventors: Koichi Yamada, Palanivel Rajan Shanmugavelayutham, Scott D. Rodgers, Barry E. Huntley, James D. Beaney, Jr., Boaz Tamir
  • Publication number: 20160180090
    Abstract: In an example, there is provided a system and method for execution profiling detection of malicious software objects. An execution profiling (EXP) engine may be provided in conjunction with a binary translation engine (BTE). Both may operate within a trusted execution environment (TEE). Because many malware objects make assumptions about memory usage of host applications, they may cause exceptions when those assumptions prove untrue. The EXP engine may proactively detect such exceptions via the BTE when the BTE performs its translation function. Thus, malicious behavior may be detected before a binary runs on a system, and remedial measures may be provided.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Applicant: McAfee, Inc.
    Inventors: Greg W. Dalcher, Koichi Yamada, Palanivel Rajan Shanmugavelayutham, Jitendra P. Singh
  • Patent number: 8886929
    Abstract: A method includes generating a chain of trust for a virtual endpoint. The virtual endpoint is associated with a layered architecture that includes layers, which include a physical layer. For each layer, a code image of a process of the layer is measured before the process is loaded to form a node of the chain of trust.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: November 11, 2014
    Assignee: Intel Corporation
    Inventors: Ned M. Smith, Palanivel Rajan Shanmugavelayutham, Rao Pitla, Ioan E. Scumpu
  • Publication number: 20140281376
    Abstract: In an embodiment, a processor includes a binary translation (BT) container having code to generate a binary translation of a first code segment and to store the binary translation in a translation cache, a host entity logic to manage the BT container and to identify the first code segment, and protection logic to isolate the BT container from a software stack. In this way, the BT container is configured to be transparent to the software stack. Other embodiments are described and claimed.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Inventors: Koichi Yamada, Palanivel Rajan Shanmugavelayutham, Scott D. Rodgers, Barry E. Huntley, James D. Beaney, JR., Boaz Tamir