Abstract: In certain aspects, a device comprises a first processing unit; a first power distribution network coupled to the first processing unit; a first decoupling capacitor coupled to the first power distribution network; a second processing unit configured to be identical to the first processing unit; a second power distribution network coupled to the second processing unit; and a second decoupling capacitor coupled to the second power distribution network, wherein the second decoupling capacitor is configured to have different effect on the second power distribution network than the first decoupling capacitor on the first power distribution network.

Abstract: Various embodiments may include methods and systems for monitoring characteristics of a system-on-a-chip. Various embodiments may include inputting, from a test data input connection, test data to a first scan chain section including a first group of logic gates located within a first region of the SoC. Various embodiments may include providing, from a first clock gate associated with the first region of the SoC, a clock signal to the first group of logic gates. Various embodiments may include measuring, using a first sensor, the characteristics at a second region of the SoC in response to providing the clock signal to the first group of logic gates. Embodiments may further include processing or analyzing measured characteristics to determine a testing result.

Abstract: Various embodiments may include methods and systems for monitoring characteristics of a system-on-a-chip. Various embodiments may include inputting, from a test data input connection, test data to a first scan chain section including a first group of logic gates located within a first region of the SoC. Various embodiments may include providing, from a first clock gate associated with the first region of the SoC, a clock signal to the first group of logic gates. Various embodiments may include measuring, using a first sensor, the characteristics at a second region of the SoC in response to providing the clock signal to the first group of logic gates. Embodiments may further include processing or analyzing measured characteristics to determine a testing result.

Abstract: In certain aspects, a device comprises a first processing unit; a first power distribution network coupled to the first processing unit; a first decoupling capacitor coupled to the first power distribution network; a second processing unit configured to be identical to the first processing unit; a second power distribution network coupled to the second processing unit; and a second decoupling capacitor coupled to the second power distribution network, wherein the second decoupling capacitor is configured to have different effect on the second power distribution network than the first decoupling capacitor on the first power distribution network.

Abstract: In one embodiment, a system including a duty-cycle-monitoring circuit is configured to receive a monitored signal having cycles that have a high portion and a low portion. The duty-cycle-monitoring circuit includes: a cascade of buffers including a first buffer, wherein the first buffer is configured to receive a first signal based on the monitored signal, a plurality of corresponding flip-flops. Each flip-flop is triggered by a second signal based on the monitored signal. The data input of each flip-flop is connected to an output of a corresponding buffer. The duty-cycle-monitoring circuit further includes a control circuit configured to determine, based on a state of the plurality of flip-flops, a measure of the duration of the high portion of a cycle of the monitored signal and determine, based on a state of the plurality of flip-flops, a measure of duration of the low portion of a cycle of the monitored signal.

Abstract: Various embodiments of methods and systems context-aware thermal management in a portable computing device (“PCD”) are disclosed. Notably, the environmental context to which a PCD is subjected may have significant impact on the PCD's thermal energy dissipation efficiency. Embodiments of the solution seek to leverage knowledge of a PCD's environmental context to modify or adjust thermal policy parameters applied within a PCD in response to a thermal event within the PCD.

Abstract: In one embodiment, a system including a duty-cycle-monitoring circuit is configured to receive a monitored signal having cycles that have a high portion and a low portion. The duty-cycle-monitoring circuit includes: a cascade of buffers including a first buffer, wherein the first buffer is configured to receive a first signal based on the monitored signal, a plurality of corresponding flip-flops. Each flip-flop is triggered by a second signal based on the monitored signal. The data input of each flip-flop is connected to an output of a corresponding buffer. The duty-cycle-monitoring circuit further includes a control circuit configured to determine, based on a state of the plurality of flip-flops, a measure of the duration of the high portion of a cycle of the monitored signal and determine, based on a state of the plurality of flip-flops, a measure of duration of the low portion of a cycle of the monitored signal.

Abstract: In one embodiment, a system has an integrated circuit (IC) device, the IC device includes a first processing unit having a first functional block that has a diversifiable sub-circuit and a result output, a second processing unit having a second functional block substantially identical to the first functional block that includes a corresponding diversifiable sub-circuit and a corresponding result output. The IC device includes a comparator adapted to compare the result output of the first functional block to the result output of the second functional block. The diversifiable sub-circuit of the first functional block operates using a first set of operating parameters. The diversifiable sub-circuit of the second functional block operates using a second set of operating parameters different from the first set of operating parameters.

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of testing error-correcting code (ECC) logic. The method includes receiving data for storage in a memory. The method further includes receiving an address indicating a location in the memory to store the data. The method further includes determining if the received address matches at least one of one or more test addresses. The method further includes operating the ECC logic in a normal mode when the received address does not match at least one of the one or more test addresses. The method further includes operating the ECC logic in a test mode when the received address does match at least one of the one or more test addresses.

Abstract: An integrated device that includes a substrate, a device level layer formed over the substrate, and interconnect portion over the device level layer. The device level layer includes a plurality of first device level cells, each first device level cell comprising a first configuration. The device level layer includes a plurality of second device level cells. At least one second device level cell includes a second configuration that is different than the first configuration. The plurality of second device level cells is located over at least one region of the integrated device comprising at least one hotspot.

Abstract: Various additional and alternative aspects are described herein. In some aspects, the present disclosure provides a method of testing error-correcting code (ECC) logic. The method includes receiving data for storage in a memory. The method further includes receiving an address indicating a location in the memory to store the data. The method further includes determining if the received address matches at least one of one or more test addresses. The method further includes operating the ECC logic in a normal mode when the received address does not match at least one of the one or more test addresses. The method further includes operating the ECC logic in a test mode when the received address does match at least one of the one or more test addresses.

Abstract: Apparatuses and methods to adjust voltage for thermal mitigation are provided. The apparatus includes a circuit, a plurality of switches configured to provide power of a power domain to the circuit, a plurality of thermal sensors disposed at different locations about the circuit and configured to detect temperatures at the different locations, and a control circuit configured to determine that one of the detected temperatures at one of the locations exceeds a temperature threshold, and in response, adjust one or more of the plurality of switches in proximity with the one location to reduce power provided to the circuit. The method includes providing power of a power domain through a plurality of switches, detecting a temperature at a location exceeding a temperature threshold, and adjusting the plurality of switches in proximity with the location to reduce the power provided, in response to the detecting the temperature exceeding the temperature threshold.

Abstract: The disclosure relates to an apparatus and method for false pass detection in lockstep dual processing core systems, triple modular redundancy (TMR) systems, or other redundant processing systems. A false pass occurs when two processing cores generate matching data outputs, both of which are in error. A false pass may occur when the processing core are both subjected to substantially the same adverse condition, such as a supply voltage drop or a sudden temperature change or gradient. The apparatus includes processing cores configured to generate first and second data outputs and first and second timing violation signals. A voter-comparator validates the first and second data outputs if they match and the first and second timing violation signals indicate no timing violations. Otherwise, the voter comparator invalidates the first and second data outputs. Validated data outputs are used for performing additional operations, and invalidated data outputs may be discarded.

Abstract: Apparatuses and methods to adjust a source voltage based on stored information are provided. The apparatus includes a circuit configured to receive power from a power source through a power distribution network, a storage medium storing data specifying one or more electrical characteristics of the circuit, and a control circuit configured to adjust a source voltage at the power source based on the data stored in the storage medium. The method includes receiving power by a circuit from a power source through a power distribution network, reading data specifying one or more electrical characteristics of the circuit from a storage medium, and adjusting a source voltage at the power source based on the data stored in the storage medium.

Abstract: Various embodiments of methods and systems context-aware thermal management in a portable computing device (“PCD”) are disclosed. Notably, the environmental context to which a PCD is subjected may have significant impact on the PCD's thermal energy dissipation efficiency. Embodiments of the solution seek to leverage knowledge of a PCD's environmental context to modify or adjust thermal policy parameters applied within a PCD in response to a thermal event within the PCD.

Abstract: A method includes generating temperature information from a plurality of temperature sensors within a computing device, wherein a first one of the temperature sensors is physically located at a first processing unit of the computing device; processing the temperature information to identify that the first temperature sensor is associated with temperature that is at or above a threshold; and assigning a processing thread to a first core of a plurality of cores of a second processing unit in response to identifying that the first temperature sensor is associated with temperature that is at or above the threshold and based at least in part on a physical distance between the first core and the first temperature sensor.

Abstract: The present disclosure is directed to mitigating voltage droops. An aspect includes outputting, by a clock module coupled to a multiplexor, a first clock signal to the multiplexor, the first clock signal generated by a clock delay component of the clock module, receiving, by the clock module, a second clock signal from a phase-locked loop (PLL), wherein the PLL outputs a third clock signal to a processor coupled to the PLL and the multiplexor, selecting, by the multiplexor, the first clock signal to output to the processor based on detecting a droop in voltage on a power supply, and selecting, by the multiplexor, the third clock signal to output to the processor based on detecting that the droop in the voltage on the power supply has passed, wherein the clock module and the processor are coupled to the power supply.

Abstract: Various aspects include a clock monitoring unit/component that is configured to repeatedly/continuously monitor a clock with the speed required to support automobile automation systems without the use of a reference clock. The clock monitoring unit/component may be configured to identify, report, and/or respond to variations or abnormalities in the monitored clock, and initiate an action to prevent the variation from causing or resulting in a failure or a vulnerability to attack. The clock monitoring unit/component in the various aspects may be configured, organized, or arranged to operate so that the circuit is immune or resistant to manipulation, modification, tampering, hacks, and other attacks.

Abstract: The disclosure relates to an apparatus and method for false pass detection in lockstep dual processing core systems, triple modular redundancy (TMR) systems, or other redundant processing systems. A false pass occurs when two processing cores generate matching data outputs, both of which are in error. A false pass may occur when the processing core are both subjected to substantially the same adverse condition, such as a supply voltage drop or a sudden temperature change or gradient. The apparatus includes processing cores configured to generate first and second data outputs and first and second timing violation signals. A voter-comparator validates the first and second data outputs if they match and the first and second timing violation signals indicate no timing violations. Otherwise, the voter comparator invalidates the first and second data outputs. Validated data outputs are used for performing additional operations, and invalidated data outputs may be discarded.

Abstract: Implementations for probabilistic thermal hotspot accommodation are disclosed herein. In an example aspect, a cell library includes cells having respective leakage current characteristics that include a leakage current variability as well as a leakage current average. In another example aspect, a method obtains cell attribute collections for respective types of multiple cells, with each of the cell attribute collections including a leakage current average and a leakage current variability corresponding to a circuit device of a respective type of cell. The method also obtains an integrated circuit design that describes how multiple circuit devices are interconnected. The method then performs a thermal analysis of the integrated circuit design using the cell attribute collections for the respective types of multiple cells including at least the leakage current variability and the leakage current average.