Abstract: A data processor (10) has a single test controller (11). The test controller (11) has a test pattern generator portion (26) and a memory verification element (27). The test pattern generator (26) generates and communicates a plurality of test patterns to the plurality of memories (12, 13, and 14) through a second storage device (17). A first storage device (16) is used to store data read from the plurality of memories (12, 13, and 14). The data from the first storage device is selectively accessed by the memory verification element (27) via the bus (31). A bit (32) or more than one bit is used to communicate to external to the processor (10) whether the memories (12, 13, and 14) are operating in an error free manner.

Abstract: A data processing system is provided having a secondary cache for performing a deferred cache load. The data processing system has a pipelined integer unit which uses an instruction prefetch unit (IPU) to maintain a steady stream of instructions to the pipeline. The (IPU) issues prefetch requests to a cache controller on a cache half-line basis. In conjunction with the prefetch request, the IPU transfers a prefetch address to a cache address memory management unit (CAMMU), for translation into a corresponding physical address. The physical address is compared with the indexed entries in a primary cache, and compared with the physical address corresponding to the single cache line stored in the secondary cache. When a prefetch miss occurs in both the primary and the secondary cache, the cache controller issues a bus transfer request to retrieve the requested cache line from an external memory.