Patents by Inventor Panayotis Andricacos

Panayotis Andricacos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7678258
    Abstract: An improved method of stabilizing wet chemical baths is disclosed. Typically such baths are used in processes for treating workpieces, for example, plating processes for plating metal onto substrates. In particular, the present invention relates to copper plating baths. More particularly, the present invention relates to the stability of copper plating baths. More particularly, the present invention relates to prevention of void formation by monitoring the accumulation of deleterious by-products in copper plating baths.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: March 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Dean S. Chung, Hariklia Deligianni, James E. Fluegel, Keith T. Kwietniak, Peter S. Locke, Darryl D. Restaino, Soon-Cheon Seo, Philippe M. Vereecken, Erick G. Walton
  • Patent number: 7581314
    Abstract: A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400° C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: September 1, 2009
    Assignee: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Panayotis Andricacos, L. Paivikki Buchwalter, John M. Cotte, Christopher Jahnes, Mahadevaiyer Krishnan, John H. Magerlein, Kenneth Stein, Richard P. Volant, James A. Tornello, Jennifer Lund
  • Patent number: 7553400
    Abstract: A plating method is capable of mechanically and electrochemically preferentially depositing a plated film in fine interconnect recesses such as trenches and via holes, and depositing the plated film to a flatter surface. The plating method including: disposing a substrate having fine interconnect recesses such that a conductive layer faces an anode; disposing a porous member between the substrate and the anode; filling a plating solution between the substrate and the anode; and repeating a process of holding the conductive layer and the porous member in contact with each other and moving the conductive layer and the porous member relatively to each other, a process of passing an electric current between the conductive layer and the anode while keeping the conductive layer still with respect to the porous member, and a process of stopping the supply of the electric current between the conductive layer and the anode.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: June 30, 2009
    Assignees: Ebara Corporation, International Business Machines Corporation (IBM)
    Inventors: Mizuki Nagai, Hiroyuki Kanda, Keiichi Kurashina, Satoru Yamamoto, Ryoichi Kimizuka, Hariklia Deligianni, Brett Baker, Keith Kwietniak, Panayotis Andricacos, Phillipe Vereecken
  • Publication number: 20080237053
    Abstract: An interconnection structure comprising a substrate having a dielectric layer with a via opening therein; wherein the opening has an underlayer of cobalt and/or nickel therein, barrier layer of an alloy of cobalt and/or nickel; and tungsten is provided.
    Type: Application
    Filed: May 27, 2008
    Publication date: October 2, 2008
    Applicant: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Steven H. Boettcher, Sandra G. Malhotra, Milan Paunovic, Craig Ransom
  • Patent number: 7202764
    Abstract: A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400° C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: April 10, 2007
    Assignee: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Panayotis Andricacos, L. Paivikki Buchwalter, John M. Cotte, Christopher Jahnes, Mahadevaiyer Krishnan, John H. Magerlein, Kenneth Stein, Richard P. Volant, James A. Tornello, Jennifer Lund
  • Publication number: 20060283709
    Abstract: Various counter-electrodes for electroplating, electrodeposition or anodizing of substrates are disclosed. According to certain embodiments, multi-segmented counter-electrodes are provided. According to additional embodiments, counter-electrodes having concave or convex top surfaces are provided. The disclosed counter-electrodes enable greater control over electrodeposition, electroetching and anodizing processes for resistive substrates, as well as more uniform plating and etching of resistive substrates. Methods for electroplating, electrodeposition or anodizing of resistive substrates using multi-segmented counter-electrodes are also provided.
    Type: Application
    Filed: June 20, 2005
    Publication date: December 21, 2006
    Applicant: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Emanuel Cooper, John Cotte, Hariklia Deligianni, Caliopo Andricacos
  • Publication number: 20060163083
    Abstract: Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.
    Type: Application
    Filed: January 21, 2005
    Publication date: July 27, 2006
    Applicant: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Donald Canaperi, Emanuel Cooper, John Cotte, Hariklia Deligianni, Laertis Economikos, Daniel Edelstein, Silvia Franz, Balasubramanian Pranatharthiharan, Mahadevaiyer Krishnan, Andrew Mansson, Erick Walton, Alan West, Caliopi Andricacos
  • Publication number: 20060164194
    Abstract: A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400° C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.
    Type: Application
    Filed: February 21, 2006
    Publication date: July 27, 2006
    Inventors: Hariklia Deligianni, Panayotis Andricacos, L. Paivikki Buchwalter, John Cotte, Christopher Jahnes, Mahadevaiyer Krishnan, John Magerlein, Kenneth Stein, Richard Volant, James Tornello, Jennifer Lund
  • Publication number: 20060163055
    Abstract: An apparatus for direct electroplating of a conductive material, such as copper, on resistive liners or substrates is provided. The apparatus includes an integrated in-situ measuring system to follow the actual progress of the front of the conductive material during plating. Feed-back of this information to a power supply allows for more precise control of the effective current density during plating.
    Type: Application
    Filed: January 27, 2005
    Publication date: July 27, 2006
    Applicant: International Business Machines Corporation
    Inventors: Philippe Vereecken, Panayotis Andricacos, Hariklia Deligianni, Keith Kwietniak, Caliopi Andricacos
  • Patent number: 7060624
    Abstract: Flared and non-flared metallized deep vias having aspect ratios of about 2 or greater are provided. Blind vias have been fabricated in silicon substrates up to a depth of about 300 microns, and flared through vias have been fabricated up to about 750 microns, the approximate thickness of a silicon substrate wafer, enabling the formation of electrical connections at either or both ends of a via. In spite of the depth and high aspect ratios attainable, the etched vias are completely filled with plated copper conductor, completing the formation of deep vias and allowing fuller use of both sides of the substrate.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: June 13, 2006
    Assignee: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Emanuel Israel Cooper, Timothy Joseph Dalton, Hariklia Deligianni, Daniel Guidotti, Keith Thomas Kwietniak, Michelle Leigh Steen, Cornelia Kang-I Tsang
  • Publication number: 20060105534
    Abstract: An inductor and a method of forming and the inductor, the method including: (a) forming a dielectric layer on a top surface of a substrate; (b) forming a lower trench in the dielectric layer; (c) forming a resist layer on a top surface of the dielectric layer; (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (e) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.
    Type: Application
    Filed: December 28, 2005
    Publication date: May 18, 2006
    Applicant: International Business Machines Corporation
    Inventors: Daniel Edelstein, Panayotis Andricacos, John Cotte, Hariklia Deligianni, John Magerlein, Kevin Petrarca, Kenneth Stein, Richard Volant
  • Publication number: 20060081885
    Abstract: Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 20, 2006
    Applicant: International Business Machines Corporation
    Inventors: Katherine Saenger, Cyril Cabral, Hariklia Deligianni, Panayotis Andricacos, Caliopi Andricacos, Philippe Vereecken, Emanuel Cooper
  • Publication number: 20060076685
    Abstract: Patterned copper structures are fabricated by selectively capping the copper employing selective etching and/or selective electroplating in the presence of a liner material. Apparatus for addressing the problem of an increased resistive path as electrolyte during electroetching and/or electroplating flows from the wafer edge inwards is provided.
    Type: Application
    Filed: November 3, 2005
    Publication date: April 13, 2006
    Applicant: International Business Machines
    Inventors: Panayotis Andricacos, Shyng-Tsong Chen, John Cotte, Hariklia Deligianni, Mahadevaiyer Krishnan, Wei-Tsu Tseng, Philippe Vereecken
  • Publication number: 20060017169
    Abstract: A process is described for the fabrication of submicton interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 26, 2006
    Applicant: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Hariklia Deligianni, John Dukovic, Daniel Edelstein, Wilma Horkans, Chao-Kun Hu, Jeffrey Hurd, Kenneth Rodbell, Cyprian Uzoh, Kwong-Hon Wong
  • Patent number: 6974531
    Abstract: A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: December 13, 2005
    Assignee: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Hariklia Deligianni, Wilma Jean Horkans, Keith T. Kwietniak, Michael Lane, Sandra G. Malhotra, Fenton Read McFeely, Conal Murray, Kenneth P. Rodbell, Philippe M. Vereecken
  • Publication number: 20050269708
    Abstract: An interconnection structure is provided wherein comprises a substrate having a dielectric layer with a via opening therein; wherein the opening has a barrier layer; and electrodeposited copper.
    Type: Application
    Filed: July 5, 2005
    Publication date: December 8, 2005
    Inventors: Panayotis Andricacos, Steven Boettcher, Fenton McFeely, Milan Paunovic
  • Patent number: 6967131
    Abstract: Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: November 22, 2005
    Assignee: International Business Machines Corp.
    Inventors: Katherine L. Saenger, Cyril Cabral, Jr., Emanuel I. Cooper, Hariklia Deligianni, Panayotis Andricacos, Philippe M. Vereecken
  • Publication number: 20050241946
    Abstract: A plating method is capable of mechanically and electrochemically preferentially depositing a plated film in fine interconnect recesses such as trenches and via holes, and depositing the plated film to a flatter surface. The plating method including: disposing a substrate having fine interconnect recesses such that a conductive layer faces an anode; disposing a porous member between the substrate and the anode; filling a plating solution between the substrate and the anode; and repeating a process of holding the conductive layer and the porous member in contact with each other and moving the conductive layer and the porous member relatively to each other, a process of passing an electric current between the conductive layer and the anode while keeping the conductive layer still with respect to the porous member, and a process of stopping the supply of the electric current between the conductive layer and the anode.
    Type: Application
    Filed: December 21, 2004
    Publication date: November 3, 2005
    Inventors: Mizuki Nagai, Hiroyuki Kanda, Keiichi Kurashina, Satoru Yamamoto, Ryoichi Kimizuka, Hariklia Deligianni, Brett Baker, Keith Kwietniak, Panayotis Andricacos, Philippe Vereecken
  • Publication number: 20050245070
    Abstract: A method of creating a multi-layered barrier for use in an interconnect, a barrier for an interconnect, and an interconnect including the barrier are disclosed. The method includes creating the multi-layered barrier in a recess of the device terminal by use of a single electroplating chemistry to enhance protection against voiding and de-lamination due to the diffusion of copper, whether by self-diffusion or electro-migration. The barrier includes at least a first layer of nickel-rich material and a second layer of copper-rich material. The barrier enables use of higher current densities for advanced complementary metal-oxide semiconductors (CMOS) designs, and extends the reliability of current CMOS designs regardless of solder selection. Moreover, this technology is easily adapted to current methods of fabricating electroplated interconnects such as C4s.
    Type: Application
    Filed: April 28, 2004
    Publication date: November 3, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Panayotis Andricacos, Tien-Jen Cheng, Emanuel Cooper, David Eichstadt, Jonathan Griffith, Randolph Knarr, Roger Quon, Erik Roggeman
  • Publication number: 20050199502
    Abstract: A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.
    Type: Application
    Filed: May 6, 2005
    Publication date: September 15, 2005
    Applicant: International Business Machines Corporation
    Inventors: Panayotis Andricacos, Hariklia Deligianni, Wilma Horkans, Keith Kwietniak, Michael Lane, Sandra Malhotra, Fenton McFeely, Conal Murray, Kenneth Rodbell, Philippe Vereecken