Patents by Inventor Pandi Chelvam Marimuthu

Pandi Chelvam Marimuthu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220375886
    Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.
    Type: Application
    Filed: August 4, 2022
    Publication date: November 24, 2022
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Pandi Chelvam Marimuthu, Andy Chang Bum Yong, Aung Kyaw Oo, Yaojian Lin
  • Patent number: 11469191
    Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.
    Type: Grant
    Filed: March 21, 2020
    Date of Patent: October 11, 2022
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Pandi Chelvam Marimuthu, Andy Chang Bum Yong, Aung Kyaw Oo, Yaojian Lin
  • Publication number: 20200219832
    Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.
    Type: Application
    Filed: March 21, 2020
    Publication date: July 9, 2020
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Pandi Chelvam Marimuthu, Andy Chang Bum Yong, Aung Kyaw Oo, Yaojian Lin
  • Patent number: 10636753
    Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: April 28, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Pandi Chelvam Marimuthu, Andy Chang Bum Yong, Aung Kyaw Oo, Yaojian Lin
  • Patent number: 10510632
    Abstract: A semiconductor device has a carrier and a semiconductor die disposed over the carrier. A dummy die is disposed over the carrier as well. A first encapsulant is deposited over the semiconductor die and dummy die. The dummy die and a first portion of the first encapsulant is backgrinded while a second portion of the first encapsulant remains covering the semiconductor die. Backgrinding the dummy die fully removes the dummy die while the second portion of the first encapsulant remains covering the semiconductor die. A second encapsulant is optionally deposited over the dummy die prior to disposing the dummy die over the carrier. A conductive pillar is optionally formed over the dummy die prior to depositing the second encapsulant. The carrier is removed to expose an active surface of the semiconductor die. A build-up interconnect structure is formed over the active surface after removing the carrier.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: December 17, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Won Kyoung Choi, Pandi Chelvam Marimuthu
  • Publication number: 20190287873
    Abstract: A semiconductor device has a carrier and a semiconductor die disposed over the carrier. A dummy die is disposed over the carrier as well. A first encapsulant is deposited over the semiconductor die and dummy die. The dummy die and a first portion of the first encapsulant is backgrinded while a second portion of the first encapsulant remains covering the semiconductor die. Backgrinding the dummy die fully removes the dummy die while the second portion of the first encapsulant remains covering the semiconductor die. A second encapsulant is optionally deposited over the dummy die prior to disposing the dummy die over the carrier. A conductive pillar is optionally formed over the dummy die prior to depositing the second encapsulant. The carrier is removed to expose an active surface of the semiconductor die. A build-up interconnect structure is formed over the active surface after removing the carrier.
    Type: Application
    Filed: March 13, 2018
    Publication date: September 19, 2019
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Won Kyoung Choi, Pandi Chelvam Marimuthu
  • Publication number: 20190088603
    Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.
    Type: Application
    Filed: November 8, 2018
    Publication date: March 21, 2019
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Pandi Chelvam Marimuthu, Andy Chang Bum Yong, Aung Kyaw Oo, Yaojian Lin
  • Patent number: 9837303
    Abstract: A semiconductor device has a modular interconnect unit or interconnect structure disposed in a peripheral region of the semiconductor die. An encapsulant is deposited over the semiconductor die and interconnect structure. A first insulating layer is formed over the semiconductor die and interconnect structure. A plurality of openings is formed in the first insulating layer over the interconnect structure. The openings have a pitch of 40 micrometers. The openings include a circular shape, ring shape, cross shape, or lattice shape. A conductive layer is deposited over the first insulating layer. The conductive layer includes a planar surface. A second insulating layer is formed over the conductive layer. A portion of the encapsulant is removed to expose the semiconductor die and the interconnect structure. The modular interconnect unit includes a vertical interconnect structure. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: December 5, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Kang Chen, Yu Gu, Pandi Chelvam Marimuthu
  • Patent number: 9355993
    Abstract: A system and method of manufacture of an integrated circuit system includes: a die having a via, the die having a top side and a bottom side; a top interconnect mounted to the via at the top side; an interconnect pillar mounted to the via at the bottom side; a device interconnect mounted to the interconnect pillar; and a base adhesive covering the interconnect pillar and the device interconnect.
    Type: Grant
    Filed: July 3, 2015
    Date of Patent: May 31, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Won Kyoung Choi, Pandi Chelvam Marimuthu
  • Patent number: 9343396
    Abstract: A semiconductor wafer contains semiconductor die. A first conductive layer is formed over the die. A resistive layer is formed over the die and first conductive layer. A first insulating layer is formed over the die and resistive layer. The wafer is singulated to separate the die. The die is mounted to a temporary carrier. An encapsulant is deposited over the die and carrier. The carrier and a portion of the encapsulant and first insulating layer is removed. A second insulating layer is formed over the encapsulant and first insulating layer. A second conductive layer is formed over the first and second insulating layers. A third insulating layer is formed over the second insulating layer and second conductive layer. A third conductive layer is formed over the third insulating layer and second conductive layer. A fourth insulating layer is formed over the third insulating layer and third conductive layer.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: May 17, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Robert C. Frye, Pandi Chelvam Marimuthu, Kai Liu
  • Patent number: 9318404
    Abstract: A semiconductor device includes a semiconductor die. An encapsulant is disposed around the semiconductor die to form a peripheral area. An interconnect structure is formed over a first surface of the semiconductor die and encapsulant. A plurality of vias is formed partially through the peripheral area of the encapsulant and offset from the semiconductor die. A portion of the encapsulant is disposed over a second surface of the semiconductor die opposite the first surface. The plurality of vias comprises a depth greater than a thickness of the portion of the encapsulant. A first portion of the plurality of vias is formed in a row offset from a side of the semiconductor die. A second portion of the plurality of vias is formed as an array of vias offset from a corner of the semiconductor die. A repair material disposed within the plurality of vias.
    Type: Grant
    Filed: February 5, 2013
    Date of Patent: April 19, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Pandi Chelvam Marimuthu, Kang Chen, Yu Gu
  • Patent number: 9224647
    Abstract: A semiconductor device has a substrate with first and second opposing surfaces. A plurality of conductive vias is formed partially through the first surface of the substrate. A first conductive layer is formed over the first surface of the substrate electrically connected to the conductive vias. A first semiconductor die is mounted over the first surface of the substrate. The first semiconductor die and substrate are mounted to a carrier. An encapsulant is deposited over the first semiconductor die, substrate, and carrier. A portion of the second surface of the substrate is removed to expose the conductive vias. An interconnect structure is formed over a surface of the substrate opposite the first semiconductor die. A second semiconductor die can be stacked over the first semiconductor die. A second semiconductor die can be mounted over the first surface of the substrate adjacent to the first semiconductor die.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: December 29, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Jun Mo Koo, Pandi Chelvam Marimuthu, Jae Hun Ku, Seung Wook Yoon
  • Publication number: 20150311180
    Abstract: A system and method of manufacture of an integrated circuit system includes: a die having a via, the die having a top side and a bottom side; a top interconnect mounted to the via at the top side; an interconnect pillar mounted to the via at the bottom side; a device interconnect mounted to the interconnect pillar; and a base adhesive covering the interconnect pillar and the device interconnect.
    Type: Application
    Filed: July 3, 2015
    Publication date: October 29, 2015
    Inventors: Won Kyoung Choi, Pandi Chelvam Marimuthu
  • Patent number: 9076724
    Abstract: A system and method of manufacture of an integrated circuit system includes: a die having a via, the die having a top side and a bottom side; a top interconnect mounted to the via at the top side; an interconnect pillar mounted to the via at the bottom side; a device interconnect mounted to the interconnect pillar; and a base adhesive covering the interconnect pillar and the device interconnect.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: July 7, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Won Kyoung Choi, Pandi Chelvam Marimuthu
  • Patent number: 9029193
    Abstract: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: May 12, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Pandi Chelvam Marimuthu, Nathapong Suthiwongsunthorn, Kock Liang Heng
  • Patent number: 8951904
    Abstract: An integrated circuit package system including: providing an integrated circuit die, forming a first layer over the integrated circuit die, forming a bridge on and in the first layer, forming a second layer on the first layer, and forming bump pads on and in the second layer, the bump pads connected to ends of the bridge.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: February 10, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Yaojian Lin, Pandi Chelvam Marimuthu
  • Patent number: 8951839
    Abstract: A semiconductor device has a semiconductor die mounted over the carrier. An encapsulant is deposited over the carrier and semiconductor die. The carrier is removed. A first interconnect structure is formed over the encapsulant and a first surface of the die. A second interconnect structure is formed over the encapsulant and a second surface of the die. A first protective layer is formed over the first interconnect structure and second protective layer is formed over the second interconnect structure prior to forming the vias. A plurality of vias is formed through the second interconnect structure, encapsulant, and first interconnect structure. A first conductive layer is formed in the vias to electrically connect the first interconnect structure and second interconnect structure. An insulating layer is formed over the first interconnect structure and second interconnect structure and into the vias. A discrete semiconductor component can be mounted to the first interconnect structure.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: February 10, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Pandi Chelvam Marimuthu
  • Patent number: 8912650
    Abstract: A semiconductor device has a semiconductor die with a first conductive layer formed over the semiconductor die. A first insulating layer is formed over the semiconductor die with a first opening in the first insulating layer disposed over the first conductive layer. A second conductive layer is formed over the first insulating layer and into the first opening over the first conductive layer. An interconnect structure is formed over the first and second conductive layers within openings of a second insulating layer. The second insulating layer is removed. The interconnect structure can be a conductive pillar or conductive pad. A bump material can be formed over the conductive pillar. A protective coating is formed over the conductive pillar or pad to a thickness less than one micrometer to reduce oxidation. The protective coating is formed by immersing the conductive pillar or pad into the bath containing tin or indium.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 16, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Won Kyoung Choi, Pandi Chelvam Marimuthu
  • Patent number: 8900929
    Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over the semiconductor die. A first insulating layer having high tensile strength and elongation is formed over the semiconductor die and encapsulant. A first portion of the first insulating layer is removed by a first laser direct ablation to form a plurality of openings in the first insulating layer. The openings extend partially through the first insulating layer or into the encapsulant. A second portion of the first insulating layer is removed by a second laser direct ablation to form a plurality of trenches in the first insulating layer. A conductive layer is formed in the openings and trenches of the first insulating layer. A second insulating layer is formed over the conductive layer. A portion of the second insulating layer is removed by a third laser direct ablation. Bumps are formed over the conductive layer.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: December 2, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Pandi Chelvam Marimuthu, Kang Chen
  • Patent number: 8810024
    Abstract: A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A modular interconnect unit is mounted over the carrier and around or in a peripheral region around the semiconductor die such that the modular interconnect unit is offset from the back surface of the semiconductor die. An encapsulant is deposited over the carrier, semiconductor die, and modular interconnect unit. A first portion of the encapsulant is removed to expose the semiconductor die and a second portion is removed to expose the modular interconnect unit. The carrier is removed. An interconnect structure is formed over the semiconductor die and modular interconnect unit. The modular interconnect unit includes a vertical interconnect structures or bumps through the semiconductor device. The modular interconnect unit forms part of an interlocking pattern around the semiconductor die.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: August 19, 2014
    Assignee: STATS ChipPAC Ltd.
    Inventors: Yaojian Lin, Pandi Chelvam Marimuthu, Kang Chen, Yu Gu