Patents by Inventor Paolo Faraboschi

Paolo Faraboschi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10725940
    Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 28, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Qiong Cai, Paolo Faraboschi, Cong Xu, Ping Chi, Sai Rahul Chalamalasetti, Andrew C. Walton
  • Patent number: 10698878
    Abstract: In some examples, a graph processing server is communicatively linked to a shared memory. The shared memory may also be accessible to a different graph processing server. The graph processing server may compute an updated vertex value for a graph portion handled by the graph processing server and flush the updated vertex value to the shared memory, for retrieval by the different graph processing server. The graph processing server may also notify the different graph processing server indicating that the updated vertex value has been flushed to the shared memory.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: June 30, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Stanko Novakovic, Kimberly Keeton, Paolo Faraboschi, Robert Schreiber
  • Patent number: 10691375
    Abstract: In one example, a memory network may control access to a shared memory that is by multiple compute nodes. The memory network may control the access to the shared memory by receiving a memory access request originating from an application executing on the multiple compute nodes and determining a priority for processing the memory access request. The priority determined by the memory network may correspond to a memory address range in the memory that is specifically used by the application.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: June 23, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Vanish Talwar, Paolo Faraboschi, Daniel Gmach, Yuan Chen, Al Davis, Adit Madan
  • Patent number: 10649829
    Abstract: In some examples, a controller includes a counter to track errors associated with a group of memory access operations, and processing logic to detect an error associated with the group of memory access operations, determine whether the detected error causes an error state change of the group of memory access operations, and cause advancing of the counter responsive to determining that the detected error causes the error state change of the group of memory access operations.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: May 12, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Derek Alan Sherlock, Shawn Walker, Paolo Faraboschi
  • Patent number: 10620861
    Abstract: Techniques for retrieving data blocks from memory devices are provided. In one aspect, a request to retrieve a block of data may be received. The block of data may be in a line in a rank of memory. The rank of memory may include multiple devices. The devices used to store the line in the rank of memory may be determined. The determined devices may be read.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: April 14, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Rajeev Balasubramonian, Paolo Faraboschi, Gregg B. Lesartre, Naveen Muralimanohar
  • Publication number: 20200097440
    Abstract: A method of computing in memory, the method including inputting a packet including data into a computing memory unit having a control unit, loading the data into at least one computing in memory micro-unit, processing the data in the computing in memory micro-unit, and outputting the processed data. Also, a computing in memory system including a computing in memory unit having a control unit, wherein the computing in memory unit is configured to receive a packet having data and a computing in memory micro-unit disposed in the computing in memory unit, the computing in memory micro-unit having at least one of a memory matrix and a logic elements matrix.
    Type: Application
    Filed: September 24, 2018
    Publication date: March 26, 2020
    Inventors: Dejan S. Milojicic, Kirk M. Bresniker, Paolo Faraboschi, John Paul Strachan
  • Publication number: 20200091930
    Abstract: Computer-implemented methods, systems, and devices to perform lossless compression of floating point format time-series data are disclosed. A first data value may be obtained in floating point format representative of an initial time-series parameter. For example, an output checkpoint of a computer simulation of a real-world event such as weather prediction or nuclear reaction simulation. A first predicted value may be determined representing the parameter at a first checkpoint time. A second data value may be obtained from the simulation. A prediction error may be calculated. Another predicted value may be generated for a next point in time and may be adjusted by the previously determined prediction error (e.g., to increase accuracy of the subsequent prediction). When a third data value is obtained, the adjusted prediction value may be used to generate a difference (e.g., XOR) for storing in a compressed data store to represent the third data value.
    Type: Application
    Filed: September 14, 2018
    Publication date: March 19, 2020
    Inventors: Anirban Nag, Naveen Muralimanohar, Paolo Faraboschi
  • Patent number: 10592431
    Abstract: According to examples, an apparatus may include a processor to address a physical memory having memory sections, in which a first set of memory sections may be shared between processes and a second set of memory sections may be specific to an individual process. The apparatus may also include a shared virtual address space register to provide translation for the first set of memory sections shared between processes and a process virtual address space register to provide translation for the second set of memory sections specific to the individual process. The translation for the second set of memory sections may be independent from the translation for the first set of memory sections.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: March 17, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Izzat El Hajj, Alexander Marshall Merritt, Gerd Zellweger, Dejan S. Milojicic, Paolo Faraboschi
  • Patent number: 10592437
    Abstract: Memory blocks are associated with each memory level of a hierarchy of memory levels. Each memory block has a matching key capability (MaKC). The MaKC of a memory block governs access to the memory block, in accordance with permissions specified by the MaKC. The MaKC of a memory block can uniquely identify the memory block across the hierarchy of memory levels, and can be globally unique across the memory blocks. An MaKC of a memory block includes a block protection key (BPK) stored with the memory block, and an execution protection key (EPK). If a provided EPK for a memory block matches the memory block's BPK upon comparison, access to the memory block is allowed according to the permissions specified by the MaKC.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: March 17, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Geoffrey Ndu, Dejan S. Milojicic, Paolo Faraboschi, Chris I. Dalton
  • Publication number: 20200073755
    Abstract: A computer system includes multiple memory array components that include respective analog memory arrays which are sequenced to implement a multi-layer process. An error array data structure is obtained for at least a first memory array component, and from which a determination is made as to whether individual nodes (or cells) of the error array data structure are significant. A determination can be made as to any remedial operations that can be performed to mitigate errors of significance.
    Type: Application
    Filed: August 28, 2018
    Publication date: March 5, 2020
    Inventors: John Paul Strachan, Catherine Graves, Dejan S. Milojicic, Paolo Faraboschi, Martin Foltin, Sergey Serebryakov
  • Patent number: 10579519
    Abstract: In some examples, each processor of a plurality of processors applies an interleave transform to perform interleaved access of a plurality of memory banks, where for any given memory address in use by the plurality of processors, applying any of the interleave transforms results in selection of a same memory bank of the plurality of memory banks and a same address within the same memory bank.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: March 3, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Mark David Lillibridge, Gary Gostin, Paolo Faraboschi, Derek Alan Sherlock, Harvey Ray
  • Patent number: 10572150
    Abstract: According to an example, a memory network includes memory nodes. The memory nodes may each include memory and control logic. The control logic may operate the memory node as a destination for a memory access invoked by a processor connected to the memory network and may operate the memory node as a router to route data or memory access commands to a destination in the memory network.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: February 25, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sheng Li, Norman Paul Jouppi, Paolo Faraboschi, Michael R. Krause
  • Publication number: 20200050553
    Abstract: According to examples, an apparatus may include a processor to address a physical memory having memory sections, in which a first set of memory sections may be shared between processes and a second set of memory sections may be specific to an individual process. The apparatus may also include a shared virtual address space register to provide translation for the first set of memory sections shared between processes and a process virtual address space register to provide translation for the second set of memory sections specific to the individual process. The translation for the second set of memory sections may be independent from the translation for the first set of memory sections.
    Type: Application
    Filed: August 13, 2018
    Publication date: February 13, 2020
    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Izzat El Hajj, Alexander Marshall Merritt, Gerd Zellweger, Dejan S. Milojicic, Paolo Faraboschi
  • Publication number: 20200042287
    Abstract: Disclosed techniques provide for dynamically changing precision of a multi-stage compute process. For example, changing neural network (NN) parameters on a per-layer basis depending on properties of incoming data streams and per-layer performance of an NN among other considerations. NNs include multiple layers that may each be calculated with a different degree of accuracy and therefore, compute resource overhead (e.g., memory, processor resources, etc.). NNs are usually trained with 32-bit or 16-bit floating-point numbers. Once trained, an NN may be deployed in production. One approach to reduce compute overhead is to reduce parameter precision of NNs to 16 or 8 for deployment. The conversion to an acceptable lower precision is usually determined manually before deployment and precision levels are fixed while deployed.
    Type: Application
    Filed: August 1, 2018
    Publication date: February 6, 2020
    Inventors: Sai Rahul Chalamalasetti, Paolo Faraboschi, Martin Foltin, Catherine Graves, Dejan S. Milojicic, Sergey Serebryakov, John Paul Strachan
  • Patent number: 10516806
    Abstract: A color image is processed into a renderable image. The color image comprises a plurality of pixels. Each pixel has colorimetry defined in a first color space. The renderable image comprises a plurality of renderable pixels defined by a device-vector in a second color space. For each pixel: a device-vector defined in the second color space is selected (301) based on the colorimetry defined in a first color space of the pixel. The device-vector comprises a plurality of elements. Each element includes an identifier and an accumulated weighting. An element of the selected device-vector is reselected (303) until the accumulated weighting (a) is greater than a threshold value (t) associated with the pixel (305). The levels for each color of the second color space (or mappings) for the currently selected (307) element of the selected device-vector is determined (309) to convert the pixel into a renderable pixel.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 24, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Juan Manuel Garcia Reyero Viñas, Paolo Faraboschi, Jan Morovic, Peter Morovic
  • Publication number: 20190324857
    Abstract: In some examples, with respect to adaptive multi-level checkpointing, a transfer parameter associated with transfer of checkpoint data from a node-local storage to a parallel file system may be ascertained for the checkpoint data stored in the node-local storage. The transfer parameter may be compared to a specified transfer parameter threshold. A determination may be made, based on the comparison of the transfer parameter to the specified transfer parameter threshold, as to whether to transfer the checkpoint data from the node-local storage to the parallel file system.
    Type: Application
    Filed: April 23, 2018
    Publication date: October 24, 2019
    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Cong XU, Itir AKGUN, Paolo FARABOSCHI
  • Patent number: 10452472
    Abstract: A dot-product engine (DPE) implemented on an integrated circuit as a crossbar array (CA) includes memory elements comprising a memristor and a transistor in series. A crossbar with N rows, M columns may have N×M memory elements. A vector input for N voltage inputs to the CA and a vector output for M voltage outputs from the CA. An analog-to-digital converter (ADC) and/or a digital-to-analog converter (DAC) may be coupled to each input/output register. Values representing a first matrix may be stored in the CA. Voltages/currents representing a second matrix may be applied to the crossbar. Ohm's Law and Kirchoff's Law may be used to determine values representing the dot-product as read from the crossbar. A portion of the crossbar may perform Error-correcting Codes (ECC) concurrently with calculating the dot-product results. ECC codes may be used to only indicate detection of errors, or for both detection and correction of results.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: October 22, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Catherine Graves, John Paul Strachan, Dejan S. Milojicic, Paolo Faraboschi, Martin Foltin, Sergey Serebryakov
  • Patent number: 10324722
    Abstract: Example implementations relate to global capabilities transferrable across node boundaries. For example, in an implementation, a switch that routes traffic between a node and global memory may receive an instruction from the node. The switch may recognize that data referenced by the instruction is a global capability, and the switch may process that global capability accordingly.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: June 18, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Dejan S Milojicic, Paolo Faraboschi, Chris I Dalton
  • Patent number: 10324644
    Abstract: Examples described herein include receiving an operation pipeline for a computing system and building a graph that comprises a model for a number of potential memory side accelerator thread assignments to carry out the operation pipeline. The computing system may comprise at least two memories and a number of memory side accelerators. Each model may comprise a number of steps and at least one step out of the number of steps in each model may comprise a function performed at one memory side accelerator out of the number of memory side accelerators. Examples described herein also include determining a cost of at least one model.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: June 18, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Kaisheng Ma, Qiong Cai, Cong Xu, Paolo Faraboschi
  • Patent number: 10303622
    Abstract: Techniques for writing data to a subset of memory devices are described. In one aspect, a block of data to be written to a line in a rank of memory may be received. The rank of memory may comprise a set of memory devices. The block of data may be compressed. The compressed block of data may be written to a subset of the memory devices that comprise the line. The unwritten portions of the line may not be used to store valid data.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: May 28, 2019
    Assignee: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
    Inventors: Rajeev Balasubramonian, Naveen Muralimanohar, Gregg B. Lesartre, Paolo Faraboschi, Jishen Zhao