Abstract: A light emitting diode (LED) array may include a first pixel and a second pixel on a substrate. The first pixel and the second pixel may include one or more tunnel junctions on one or more LEDs. The LED array may include a first trench between the first pixel and the second pixel. The trench may extend to the substrate.

Abstract: A light emitting diode (LED) array may include a first pixel and a second pixel on a substrate. The first pixel and the second pixel may include one or more tunnel junctions on one or more LEDs. The LED array may include a first trench between the first pixel and the second pixel. The trench may extend to the substrate.

Abstract: Embodiments of the invention include a III-nitride light emitting layer disposed between an n-type region and a p-type region, a III-nitride layer including a nanopipe defect, and a nanopipe terminating layer disposed between the III-nitride light emitting layer and the III-nitride layer comprising a nanopipe defect. The nanopipe terminates in the nanopipe terminating layer.

Abstract: A light emitting diode (LED) array may include a first pixel and a second pixel on a substrate. The first pixel and the second pixel may include one or more tunnel junctions on one or more LEDs. The LED array may include a first trench between the first pixel and the second pixel. The trench may extend to the substrate.

Abstract: A light emitting diode (LED) device may include an n-type layer formed on a transparent substrate. A photoluminescent (PL) in the n-type layer quantum well (QW) and an electroluminescent (EL) QW may be formed on the n-type layer. The PL QW and the EL QW may be separated from one another by a portion of the n-type layer. A p-type layer may be formed on the EL QW. Trenches may be formed extending into the n-type layer, the trenches defining an emitting area. A passivation material may be formed on sidewalls of the trenches and n-type contacts may be formed therein. A p-type contact may be formed on an upper surface of the p-type layer. A dichroic mirror may be formed on at least a lower surface of the transparent substrate.

Abstract: A light emitting diode (LED) array may include a first pixel and a second pixel on a substrate. The first pixel and the second pixel may include one or more tunnel junctions on one or more LEDs. The LED array may include a first trench between the first pixel and the second pixel. The trench may extend to the substrate.

Abstract: Embodiments of the invention include a III-nitride light emitting layer disposed between an n-type region and a p-type region, a III-nitride layer including a nanopipe defect, and a nanopipe terminating layer disposed between the III-nitride light emitting layer and the III-nitride layer comprising a nanopipe defect. The nanopipe terminates in the nanopipe terminating layer.

Abstract: A light emitting diode (LED) device may include an n-type layer formed on a transparent substrate. A photoluminescent (PL) in the n-type layer quantum well (QW) and an electroluminescent (EL) QW may be formed on the n-type layer. The PL QW and the EL QW may be separated from one another by a portion of the n-type layer. A p-type layer may be formed on the EL QW. Trenches may be formed extending into the n-type layer, the trenches defining an emitting area. A passivation material may be formed on sidewalls of the trenches and n-type contacts may be formed therein. A p-type contact may be formed on an upper surface of the p-type layer. A dichroic mirror may be formed on at least a lower surface of the transparent substrate.

Abstract: A device may include a first light emitting diode (LED) on a first surface of a substrate, a first tunnel junction on the first LED a first semiconductor layer on the first tunnel junction, and a conformal dielectric layer on at least a sidewall of the LED and the first surface of the substrate.

Abstract: A light emitting diode (LED) array may include a first pixel and a second pixel on a substrate. The first pixel and the second pixel may include one or more tunnel junctions on one or more LEDs. The LED array may include a first trench between the first pixel and the second pixel. The trench may extend to the substrate.

Abstract: Embodiments of the invention include a III-nitride light emitting layer disposed between an n-type region and a p-type region, a III-nitride layer including a nanopipe defect, and a nanopipe terminating layer disposed between the III-nitride light emitting layer and the III-nitride layer comprising a nanopipe defect. The nanopipe terminates in the nanopipe terminating layer.

Abstract: Embodiments of the invention include a III-nitride light emitting layer disposed between an n-type region and a p-type region, a III-nitride layer including a nanopipe defect, and a nanopipe terminating layer disposed between the III-nitride light emitting layer and the III-nitride layer comprising a nanopipe defect. The nanopipe terminates in the nanopipe terminating layer.

Abstract: Embodiments of the invention include a III-nitride light emitting layer disposed between an n-type region and a p-type region, a III-nitride layer including a nanopipe defect, and a nanopipe terminating layer disposed between the III-nitride light emitting layer and the III-nitride layer comprising a nanopipe defect. The nanopipe terminates in the nanopipe terminating layer.

Abstract: A semiconductor structure comprises a III-nitride light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure further comprises a curvature control layer grown on a first layer. The curvature control layer is disposed between the n-type region and the first layer. The curvature control layer has a theoretical a-lattice constant less than the theoretical a-lattice constant of GaN. The first layer is a substantially single crystal layer.

Abstract: A semiconductor structure comprises a III-nitride light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure further comprises a curvature control layer grown on a first layer. The curvature control layer is disposed between the n-type region and the first layer. The curvature control layer has a theoretical a-lattice constant less than the theoretical a-lattice constant of GaN. The first layer is a substantially single crystal layer.