Patents by Inventor Paritosh M. Kulkarni

Paritosh M. Kulkarni has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Predicting for all branch instructions in a bunch based on history register updated once for all of any taken branches in a bunch
    Patent number: 6055629
    Abstract: A method for a prediction correlation between a first group of branch instructions in a bunch of instructions and a second group of branch instructions in a bunch of instructions is disclosed. The method includes indicating a direction of a plurality of branch instructions in a bunch of instructions. More particularly, the method includes building an address composed of an instruction fetch address and bits in a history register. The method accesses a bunch of instructions using the fetch address and accesses a prediction bits set from a branch history table using the composed address. The accessed bunch of instructions are processed. Further, the history register and the branch history table are updated to correlate a first group of a branch instructions in the accessed bunch of instructions to a second group of branch instructions in a next group of branch instructions in the bunch of instructions.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: April 25, 2000
    Assignee: Fujitsu, Ltd.
    Inventors: Paritosh M. Kulkarni, Richard Reeve, Nirmal R. Saxena
  • Branch prediction based on correlation between sets of bunches of branch instructions
    Patent number: 5896529
    Abstract: A method for a prediction correlation between a first group of branch instructions in a bunch of instructions and a second group of branch instructions in a bunch of instructions is disclosed. The method includes indicating a direction of a plurality of branch instructions in a bunch of instructions. More particularly, the method includes building an address composed of an instruction fetch address and bits in a history register. The method accesses a bunch of instructions using the fetch address and accesses a prediction bits set from a branch history table using the composed address. The accessed bunch of instructions are processed. Further, the history register and the branch history table are updated to correlate a first group of a branch instructions in the accessed bunch of instructions to a second group of branch instructions in a next group of branch instructions in the bunch of instructions.
    Type: Grant
    Filed: December 24, 1997
    Date of Patent: April 20, 1999
    Assignee: Fujitsu Ltd.
    Inventors: Paritosh M. Kulkarni, Richard Reeve, Nirmal R. Saxena
  • Method and apparatus for a single history register based branch predictor in a superscalar microprocessor
    Patent number: 5742805
    Abstract: Methods and apparati predict whether conditional branch computer instructions should be taken or not taken. A history register is maintained to record the history of groups of instructions, updated only once for each group. The history register and an address of one of the bytes of one of the instructions in each group are appended or otherwise combined to create an address to a table of two-bit saturating counters. The value of one of the bits of the counter at the address created is used for predicting all the conditional branch instructions for each branch in the group.
    Type: Grant
    Filed: February 15, 1996
    Date of Patent: April 21, 1998
    Assignee: Fujitsu Ltd.
    Inventors: Paritosh M. Kulkarni, Richard Reeve, Nirmal R. Saxena