Patents by Inventor Patrick A. La Fratta

Patrick A. La Fratta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220179590
    Abstract: Various embodiments described herein provide for selectively sending a cache-based read command, such as a speculative read (SREAD) command in accordance with a Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) memory protocol, to a memory sub-system.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 9, 2022
    Inventors: Dhawal Bavishi, Patrick A. La Fratta
  • Publication number: 20220147262
    Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 12, 2022
    Inventors: Robert M. Walker, Paul Rosenfeld, Patrick A. La Fratta
  • Publication number: 20220113887
    Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a data migration component, such as a driver, for facilitating the transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may indicate the data migration operation to a second component (e.g., a controller) of the memory system. The second component may initiate the transfer of data between the first memory device and the second memory device based on the receiving the indication of the data migration operation. In some cases, the transfer of data between the first memory device and the second memory device may occur within the memory system without being transferred through a host device.
    Type: Application
    Filed: October 26, 2021
    Publication date: April 14, 2022
    Inventors: Robert M. Walker, Paul Rosenfeld, Patrick A. La Fratta
  • Patent number: 11301383
    Abstract: A method is described for managing the issuance and fulfillment of memory commands. The method includes receiving, by a cache controller of a memory subsystem, a first memory command corresponding to a set of memory devices. In response, the cache controller adds the first memory command to a cache controller command queue such that the cache controller command queue stores a first set of memory commands and sets a priority of the first memory command to either a high or low priority based on (1) whether the first memory command is of a first or second type and (2) an origin of the first memory command.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: April 12, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Patrick A. La Fratta, Cagdas Dirik, Laurent Isenegger, Robert M. Walker
  • Patent number: 11288214
    Abstract: Apparatuses and methods related to command selection policy for electronic memory or storage are described. Commands to a memory controller may be prioritized based on a type of command, a timing of when one command was received relative to another command, a timing of when one command is ready to be issued to a memory device, or some combination of such factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read commands) are prioritized over other types of commands (e.g., write commands). The policy may employ exceptions to such an FRFCFS policy based on dependencies or relationships among or between commands. An example can include inserting a command into a priority queue based on a category corresponding to respective commands, and iterating through a plurality of priority queues in order of priority to select a command to issue.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Patrick A. La Fratta, Robert M. Walker
  • Patent number: 11262946
    Abstract: Various embodiments described herein provide for selectively sending a cache-based read command, such as a speculative read (SREAD) command in accordance with a Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) memory protocol, to a memory sub-system.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dhawal Bavishi, Patrick A. La Fratta
  • Patent number: 11256437
    Abstract: Apparatuses and methods for performing data migration operations are disclosed. An apparatus may include at least two interfaces, a first interface supporting data migration operations and a second interface supporting access operations associated with a host device. In some cases, the access operations may be a signal or protocol according to an industry standard or specification (e.g., a DRAM interface specification). The second interface may facilitate supporting industry standard applications, while the first interface supporting data migration operations may provide improved bandwidth for migrating data within the apparatus. The apparatus may include a buffer coupled with the interface and a bank cluster including two or more banks of memory cells. When a host device addresses a bank of the bank cluster, the apparatus may perform one or more data migration operations using the buffer and a different bank of the bank cluster.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Robert M. Walker, Paul Rosenfeld, Patrick A. La Fratta
  • Publication number: 20220050616
    Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a component, such as a controller, for facilitating a transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may receive an indication of the data migration operation from a host device and may initiate a transfer of data between the first and second memory devices. The controller may include one or more buffers to store data being transferred between the first and second memory devices. In some cases, the transfer of data between the first and second memory devices may occur within the memory system and without being transferred through the host device.
    Type: Application
    Filed: October 27, 2021
    Publication date: February 17, 2022
    Inventors: Robert M. Walker, Paul Rosenfeld, Patrick A. La Fratta
  • Publication number: 20220027095
    Abstract: Initialization is performed based on the commands received at the command queue. To perform initialization, a bank touch count list that includes a list of banks being accessed by the commands and a bank touch count for each of the banks in the list is updated. The bank touch count identifies the number of commands accessing each of the banks. The bank touch count list is updated by assigning a bank priority rank to each of the banks based on their bank touch count, respectively. Once initialized, the commands in the command queue are scheduled by inserting each of the commands into priority queues based on the bank touch count list.
    Type: Application
    Filed: October 11, 2021
    Publication date: January 27, 2022
    Inventors: Patrick A. La Fratta, Robert Walker
  • Publication number: 20220019533
    Abstract: A method is described for managing the issuance and fulfillment of memory commands. The method includes receiving, by a cache controller of a memory subsystem, a first memory command corresponding to a set of memory devices. In response, the cache controller adds the first memory command to a cache controller command queue such that the cache controller command queue stores a first set of memory commands and sets a priority of the first memory command to either a high or low priority based on (1) whether the first memory command is of a first or second type and (2) an origin of the first memory command.
    Type: Application
    Filed: July 14, 2020
    Publication date: January 20, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Patrick A. La Fratta, Cagdas Dirik, II, Laurent Isenegger, Robert M. Walker
  • Publication number: 20220019360
    Abstract: A method is described that includes receiving a plurality of streams of memory requests and each stream is associated with a source. The method further includes determining a bandwidth allocation for each stream, wherein each allocation represents a portion of a total bandwidth of a memory component managed by the subsystem and each allocation indicates a priority of a corresponding stream based on a corresponding source of each stream and assigning a set of credits to each stream based on the bandwidth allocations. The method also includes determining a memory command from a queue for issuance, wherein each memory command in the queue is associated with a stream and determining the memory command is based on the credits assigned to each stream such that commands associated with a stream with a higher number of credits is given priority for issuance over commands associated with a stream with a lower number.
    Type: Application
    Filed: July 14, 2020
    Publication date: January 20, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Patrick A. La Fratta, Robert M. Walker
  • Patent number: 11182090
    Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a component, such as a controller, for facilitating a transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may receive an indication of the data migration operation from a host device and may initiate a transfer of data between the first and second memory devices. The controller may include one or more buffers to store data being transferred between the first and second memory devices. In some cases, the transfer of data between the first and second memory devices may occur within the memory system and without being transferred through the host device.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: November 23, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Robert M. Walker, Paul Rosenfeld, Patrick A. La Fratta
  • Patent number: 11175859
    Abstract: A method is described for managing issuance of memory commands. The method includes determining whether a number of high priority commands from a cache controller meets a first threshold. In response to meeting the first threshold, a second threshold, which indicates a maximum number of low priority commands allowed in a low latency memory command queue, is set to a first value. In response to not meeting the first threshold, the second threshold is set to a second value. The method further selects a memory command for issuance from the cache controller command queue, wherein the memory command is a high priority memory command when the number of low priority memory commands stored in the low latency memory controller command queue meets the second threshold and is a low priority memory command when the number of low priority memory commands does not meet the second threshold.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: November 16, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Patrick A. La Fratta, Laurent Isenegger, Robert M. Walker
  • Patent number: 11163473
    Abstract: Methods, systems, and devices for performing data migration operations using a memory system are described. The memory system may include a data migration component, such as a driver, for facilitating the transfer of data between a first memory device that may implement a first memory technology (e.g., having a relatively fast access speed) and a second memory device that may implement a second memory technology (e.g., having a relatively large capacity). The component may indicate the data migration operation to a second component (e.g., a controller) of the memory system. The second component may initiate the transfer of data between the first memory device and the second memory device based on the receiving the indication of the data migration operation. In some cases, the transfer of data between the first memory device and the second memory device may occur within the memory system without being transferred through a host device.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Robert M. Walker, Paul Rosenfeld, Patrick A. La Fratta
  • Patent number: 11157412
    Abstract: Various embodiments described herein provide for selectively sending a read command, such as a speculative read (SREAD) command in accordance with a Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) memory protocol, to a memory sub-system based on a predicted row status of a given memory device (e.g., random access memory (RAM)-based cache) of the memory sub-system.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Patrick A. La Fratta, Dhawal Bavishi
  • Patent number: 11144240
    Abstract: Initialization is performed based on the commands received at the command queue. To perform initialization, a bank touch count list that includes a list of banks being accessed by the commands and a bank touch count for each of the banks in the list is updated. The bank touch count identifies the number of commands accessing each of the banks. The bank touch count list is updated by assigning a bank priority rank to each of the banks based on their bank touch count, respectively. Once initialized, the commands in the command queue are scheduled by inserting each of the commands into priority queues based on the bank touch count list.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: October 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Patrick A. La Fratta, Robert Walker
  • Patent number: 11106389
    Abstract: The present disclosure describes data transfer in a memory device from sensing circuitry to controller. An example apparatus includes a controller coupled to a memory device. The controller is configured to execute a command to transfer data from a latch component to a register file in the controller. The memory device includes an array of memory cells and the latch component is coupled to rows of the array via a plurality of columns of the memory cells. The latch component includes a latch selectably coupled to each of the columns and configured to implement the command to transfer the data. The memory device includes a data line to couple the latch component to the register file to transfer the data. The controller is configured to couple to the data line and the register file to perform a write operation on the transferred data to the register file in the controller.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: August 31, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Patrick A. La Fratta, James J. Shawver
  • Publication number: 20210227361
    Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.
    Type: Application
    Filed: March 17, 2021
    Publication date: July 22, 2021
    Inventors: Patrick A. La Fratta, Robert Walker, Chandrasekhar Nagarajan
  • Publication number: 20210223999
    Abstract: Commands in a command queue are received and scheduled. For each of the commands, scheduling includes determining an age of a command based on an entrance time of the command in the command queue. When the age of the command satisfies a first threshold, marking all other commands in the command queue as not issuable when the command is a deterministic command, and marking all other commands in the command queue as not issuable when the command is a non-deterministic command and the intermediate command queue is not empty. Scheduling the command further includes determining whether the command is a read command and marking the command as not issuable when the command is a non-deterministic read command and the intermediate command queue is empty.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventors: Patrick A. La Fratta, Robert Walker
  • Publication number: 20210157517
    Abstract: Various embodiments described herein provide for selectively sending a cache-based read command, such as a speculative read (SREAD) command in accordance with a Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) memory protocol, to a memory sub-system.
    Type: Application
    Filed: November 25, 2019
    Publication date: May 27, 2021
    Inventors: Dhawal Bavishi, Patrick A. La Fratta