Abstract: In a built-in self test ("BIST") circuit for on-chip testing of an integrated circuit memory, a control logic circuit is responsive to an external signal on a test select pin for controlling the BIST operations of the major circuit groups thereof. The major circuit groups include an address PRPG (pseudo-random pattern generator), which selectively furnishes test addresses or mission addresses to the memory; a data PRPG, which selectively furnishes test data or mission data to the memory; a PSA (parallel signature analyzer) PRPG, which furnishes mission data from the memory in normal mode and determines a signature in test mode; and a decoder, which compares the signature determined by the PSA PRPG with a known correct signature and sets a flag to indicate memory pass/fail. The BIST circuit is modular and extendable for any N-word by M-bit memory.

Abstract: An architecture and device for testing mixed analog and digital VLSI circuits, wherein the digital circuit portions of the chip are grouped into a digital block, and the analog circuit protions of the chip are= grouped into an analog block. Analog signals are provided to the digital block through an A/D transducer, and digital signals are provided to the analog block through a D/A transducer. The analog and digital blocks may be isolated from each other by a digital input multiplexer disposed between the A/D transducer and the digital block, and by an analog input multiplexer disposed between the D/A transducer and the analog block. To minimize the number of pins required to implement the architecture, multiplexers are connected to accessed circuit nodes in the analog block and the digital block for selectively communicating signals from the accessed nodes to external output pins.

Abstract: A testable integrated circuit contains additional circuitry which defines--when operable in a test mode--a plurality of scan paths in each of which are connected in series a plurality of bistable elements (specifically, special scan path flip-flops) isolated from the integrated circuit combinational circuits. The input and output ends of these scan paths are connected by multi-level demultiplexer and multiplexer arrangements with the input and output pins, respectively, of the integrated circuit. The last level demultiplexer and the last level multiplexer include first groups of connections with the input and output ends of the scan paths, respectively, and second groups of connections with the input and output ends of the mission logic. The demultiplexers, the multiplexers and the scan path flip-flops are operable between mission and test modes upon the application of a mode control signal thereto.

Abstract: Built-in test apparatus is provided for testing the overall functional operation of a microprocessor system which has microprocessor, RAM, PROM, address latch, I/O, timer, multiple bus arbitration and other circuits in it. To the microprocessor system are added a pseudo-random pattern generator (PRPG), a signature register (SR), supplemental control logic, serial and parallel I/O port test logic and an LED display. The system PROM is programmed with test instructions. Test input data is provided by the test instructions and the PRPG. Test output data is processed by the SR and the system microprocessor, and the test results are presented on the display.

Abstract: A device for testing a digital electronic circuit, having a first BILBO for generating a pseudo-random test pattern, a second BILBO for analyzing a parallel-input signature, a decoder and at least one status indicator for indicating the status of a circuit under test.