Patents by Inventor Patrick Valdenaire

Patrick Valdenaire has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10997107
    Abstract: A system on chip includes an interconnect circuit including at least p input interfaces and at least k output interfaces, p source devices respectively coupled to the p input interfaces and k access ports respectively coupled to the k output interfaces and belonging to a target that includes one or more target devices. Each source device is configured to deliver transactions to the target via one of the access ports. An associated memory of each access port is configured to temporarily store the transactions received by the access port. The target is configured to deliver, for each access port, a fill signal representative of a current fill level of its associated memory. A control circuit is configured to receive the fill signals from the access ports and select the access ports eligible to receive a transaction depending on the current fill levels.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: May 4, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Patent number: 10740141
    Abstract: A system on chip includes an interconnect circuit having an input interface and a number of output interfaces. A source device is coupled to the input interface. A target device includes a sectorized addressable memory space and a number of access ports respectively coupled to the output interfaces. The source device is configured to deliver a transaction containing an address word to the target device.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: August 11, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Patent number: 10698843
    Abstract: An interconnect circuit includes a plurality of input interfaces and a plurality of output interfaces. A plurality of source devices are respectively coupled to the input interfaces. A target device has a plurality of access ports respectively coupled to the output interfaces. Each source device is configured to deliver transactions to the target device. Programmable control circuit is configured to deliver, to the interconnect circuit, a control word designating an access port assigned to this source device. The interconnect circuit is configured to route the transaction from the corresponding input interface to the output interface that is coupled to this access port and to deliver the transaction to the access port, the content of each transaction delivered to an access port being identical to the content of the corresponding transaction delivered by the source equipment whatever the selected access port.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: June 30, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Publication number: 20200174964
    Abstract: A system includes a plurality of items of master equipment, each having a programing interface, and a plurality of slave equipment. An interconnect circuit is coupled between the items of master equipment and the items of slave equipment. Each transaction is assigned an attribute capable of taking on at least two attribute values corresponding to at least two states for the master equipment. Each item of slave equipment is associated with an identifier capable of taking on at least two values corresponding respectively to at least two properties for the slave equipment. Each item of master equipment automatically inherits the property of its programing interface. A filtering circuit is configured to, in the presence of a transaction intended for an item of slave equipment, compare the corresponding attribute value with an identifier value of the intended slave equipment and reject or not reject the transaction based on the comparison.
    Type: Application
    Filed: November 14, 2019
    Publication date: June 4, 2020
    Inventors: Emmanuel Ardichvili, Laurent Lestringand, Patrick Valdenaire
  • Publication number: 20200026679
    Abstract: A system on chip includes an interconnect circuit including at least p input interfaces and at least k output interfaces, p source devices respectively coupled to the p input interfaces and k access ports respectively coupled to the k output interfaces and belonging to a target that includes one or more target devices. Each source device is configured to deliver transactions to the target via one of the access ports. An associated memory of each access port is configured to temporarily store the transactions received by the access port. The target is configured to deliver, for each access port, a fill signal representative of a current fill level of its associated memory. A control circuit is configured to receive the fill signals from the access ports and select the access ports eligible to receive a transaction depending on the current fill levels.
    Type: Application
    Filed: July 8, 2019
    Publication date: January 23, 2020
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Publication number: 20190317799
    Abstract: A system on chip includes an interconnect circuit having an input interface and a number of output interfaces. A source device is coupled to the input interface. A target device includes a sectorized addressable memory space and a number of access ports respectively coupled to the output interfaces. The source device is configured to deliver a transaction containing an address word to the target device.
    Type: Application
    Filed: March 22, 2019
    Publication date: October 17, 2019
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Publication number: 20190266108
    Abstract: An interconnect circuit includes a plurality of input interfaces and a plurality of output interfaces. A plurality of source devices are respectively coupled to the input interfaces. A target device has a plurality of access ports respectively coupled to the output interfaces. Each source device is configured to deliver transactions to the target device. Programmable control circuit is configured to deliver, to the interconnect circuit, a control word designating an access port assigned to this source device. The interconnect circuit is configured to route the transaction from the corresponding input interface to the output interface that is coupled to this access port and to deliver the transaction to the access port, the content of each transaction delivered to an access port being identical to the content of the corresponding transaction delivered by the source equipment whatever the selected access port.
    Type: Application
    Filed: February 13, 2019
    Publication date: August 29, 2019
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Patent number: 7480846
    Abstract: The invention relates to the domain of turbo decoders. Such a decoder comprises a first decoder (14) and a second decoder (16), each decoder being able to calculate extrinsic output data from extrinsic input data coming from the other decoder. The decoding circuit according to the invention comprises a single memory (31) for storing the extrinsic data. When a decoder calculates an extrinsic output data from an extrinsic input data coming from the other decoder and stored in the single memory at a certain address, this extrinsic output data is then written at this same address.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: January 20, 2009
    Assignee: ST Wireless SA
    Inventors: S├ębastien Charpentier, Patrick Valdenaire
  • Publication number: 20050180513
    Abstract: The invention relates to the domain of turbo decoders. Such a decoder comprises a first decoder (14) and a second decoder (16), each decoder being able to calculate extrinsic output data from extrinsic input data coming from the other decoder. The decoding circuit according to the invention comprises a single memory (31) for storing the extrinsic data When a decoder calculates an extrinsic output data from an extrinsic input data coming from the other decoder and stored in the single memory at a certain address, this extrinsic output data is then written at this same address.
    Type: Application
    Filed: May 7, 2003
    Publication date: August 18, 2005
    Inventors: Sebastien Charpentier, Patrick Valdenaire
  • Patent number: 5677687
    Abstract: The present invention is directed to a system and methodology where virtually no DC power dissipation is used during keyboard scanning or key closure. This is done by replacing the passive pull-up (or pull down) resistors of previous schemes by input/output (I/O) circuits with repeaters and utilizing a scanning protocol and methodology which take advantage of the bidirectional I/O devices with repeaters. In a preferred embodiment, a plurality of CMOS bidirectional I/O circuits with repeaters are used, one for each row and column line in a switch matrix. A low power, switch activation scanner circuit determines activation of a switch. The circuit is coupled to or may include a plurality of switches, arranged in rows and columns, each row output line intersecting each column output line at a different node, for coupling a first row to a first column at a first node when a first switch of the plurality of switches is activated.
    Type: Grant
    Filed: July 8, 1996
    Date of Patent: October 14, 1997
    Assignee: VLSI Technology, Inc.
    Inventor: Patrick Valdenaire
  • Patent number: 5455582
    Abstract: A digital-to-analog converter of the R/2R ladder type is composed of two individually asymmetric ladders symmetrically coupled to a differential amplifier. Switch means in the shunt arms of the ladders are controlled so that the same number of shunt arms are connected to each of a pair of input or output nodes irrespective of the value of the controlling digital signal. The most significant shunt arm in each ladder may be configured as an equivalent of that part of the respective ladder extending from the respective stage node towards the least significant end of the ladder.
    Type: Grant
    Filed: December 17, 1992
    Date of Patent: October 3, 1995
    Assignee: ULSI Technology, Inc.
    Inventor: Patrick Valdenaire
  • Patent number: 5059978
    Abstract: A digital to analog converter for the conversion of a digital signal into a corresponding analog signal. The converter has a resistive string comprising a string of first resistive segments having between segments selectable nodes including intermediate nodes wherein consecutive intermediate nodes are separated by a respective plurality of said segments. Switches provide selective coupling of at least one of the selectable nodes to an output. A decoder is responsive to the digital signal for controlling the switches. In order to reduce the output impedance of the converter and to reduce variation in the output impedance with the position of the selected node at least one auxiliary string of second resistive segments is coupled in parallel with the resistive string, providing between intermediate nodes substantially lower impedance than the respective first segments.
    Type: Grant
    Filed: December 20, 1990
    Date of Patent: October 22, 1991
    Assignee: VLSI Technology, Inc.
    Inventor: Patrick Valdenaire