Patents by Inventor Paul B. Fischer

Paul B. Fischer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10790332
    Abstract: Techniques to fabricate an RF filter using 3 dimensional island integration are described. A donor wafer assembly may have a substrate with a first and second side. A first side of a resonator layer, which may include a plurality of resonator circuits, may be coupled to the first side of the substrate. A weak adhesive layer may be coupled to the second side of the resonator layer, followed by a low-temperature oxide layer and a carrier wafer. A cavity in the first side of the resonator layer may expose an electrode of the first resonator circuit. An RF assembly may have an RF wafer having a first and a second side, where the first side may have an oxide mesa coupled to an oxide layer. A first resonator circuit may be then coupled to the oxide mesa of the first side of the RF wafer.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Bruce A. Block, Paul B. Fischer, Nebil Tanzi, Gregory Chance, Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic
  • Publication number: 20200303371
    Abstract: Disclosed herein are integrated circuit structures, packages, and devices that include resistors and/or capacitors which may be provided on the same substrate/die/chip as III-N devices, e.g., III-N transistors. An integrated circuit structure, comprising a base structure comprising a III-N material, the base structure having a conductive region of a doped III-N material. The IC structure further comprises a first contact element, including a first conductive element, a dielectric element, and a second conductive element, wherein the dielectric element is between the first conductive element and the second conductive element, and wherein the first conductive element is between the conductive region and the dielectric element. The IC structure further comprises a second contact element electrically coupled to the first contact element via the conductive region.
    Type: Application
    Filed: March 22, 2019
    Publication date: September 24, 2020
    Applicant: Intel Corporation
    Inventors: Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Marko Radosavljevic, Johann Christian Rode, Paul B. Fischer, Walid M. Hafez
  • Publication number: 20200295166
    Abstract: Techniques are disclosed for forming a heterojunction bipolar transistor (HBT) that includes a laterally grown epitaxial (LEO) base layer that is disposed between corresponding emitter and collector layers. Laterally growing the base layer of the HBT improves electrical and physical contact between electrical contacts to associated portions of the HBT device (e.g., a collector). By improving the quality of electrical and physical contact between a layer of an HBT device and corresponding electrical contacts, integrated circuits using HBTs are better able to operate at gigahertz frequency switching rates used for modern wireless communications.
    Type: Application
    Filed: September 30, 2016
    Publication date: September 17, 2020
    Applicant: INTEL CORPORATION
    Inventors: SANSAPTAK DASGUPTA, MARKO RADOSAVLJEVIC, HAN WUI THEN, PAUL B. FISCHER
  • Publication number: 20200294932
    Abstract: IC structures that include transmission line structures to be integrated with III-N devices are disclosed. An example transmission line structure includes a transmission line of an electrically conductive material provided above a stack of a III-N semiconductor material and a polarization material. The transmission line structure further includes means for reducing electromagnetic coupling between the line and charge carriers present below the interface of the polarization material and the III-N semiconductor material. In some embodiments, said means include a shield material of a metal or a doped semiconductor provided over portions of the polarization material that are under the transmission line. In other embodiments, said means include dopant atoms implanted into the portions of the polarization material that are under the transmission line, and into at least an upper portion of the III-N semiconductor material under such portions of the polarization material.
    Type: Application
    Filed: March 15, 2019
    Publication date: September 17, 2020
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Nidhi Nidhi, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
  • Publication number: 20200295172
    Abstract: Disclosed herein are IC structures, packages, and device assemblies with III-N transistors that include additional materials, referred to herein as “stressor materials,” which may be selectively provided over portions of polarization materials to locally increase or decrease the strain in the polarization material. Providing a compressive stressor material may decrease the tensile stress imposed by the polarization material on the underlying portion of the III-N semiconductor material, thereby decreasing the two-dimensional electron gas (2DEG) and increasing a threshold voltage of a transistor. On the other hand, providing a tensile stressor material may increase the tensile stress imposed by the polarization material, thereby increasing the 2DEG and decreasing the threshold voltage. Providing suitable stressor materials enables easier and more accurate control of threshold voltage compared to only relying on polarization material recess.
    Type: Application
    Filed: March 11, 2019
    Publication date: September 17, 2020
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Nidhi Nidhi, Rahul Ramaswamy, Paul B. Fischer, Walid M. Hafez, Johann Christian Rode
  • Publication number: 20200279932
    Abstract: Disclosed herein are IC structures, packages, and devices that include planar III-N transistors with wrap-around gates and/or one or more wrap-around source/drain (S/D) contacts. An example IC structure includes a support structure (e.g., a substrate) and a planar III-N transistor. The transistor includes a channel stack of a III-N semiconductor material and a polarization material, provided over the support structure, a pair of S/D regions provided in the channel stack, and a gate stack of a gate dielectric material and a gate electrode material provided over a portion of the channel stack between the S/D regions, where the gate stack at least partially wraps around an upper portion of the channel stack.
    Type: Application
    Filed: March 1, 2019
    Publication date: September 3, 2020
    Applicant: Intel Corporation
    Inventors: Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Johann Christian Rode, Paul B. Fischer, Walid M. Hafez
  • Patent number: 10763248
    Abstract: The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300 mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Sansaptak W. Dasgupta, Marko Radosavljevic, Han Wui Then, Ravi Pillarisetty, Kimin Jun, Patrick Morrow, Valluri R. Rao, Paul B. Fischer, Robert S. Chau
  • Publication number: 20200273751
    Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor layer transfer. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by, first, depositing a semiconductor material layer, a portion of which will later serve as a channel material of the non-III-N transistor, on a support structure different from that on which the III-N semiconductor material for the III-N transistor is provided, and then performing layer transfer of said semiconductor material layer to the support structure with the III-N material, e.g., by oxide-to-oxide bonding, advantageously enabling implementation of both types of transistors on a single support structure.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Paul B. Fischer
  • Publication number: 20200273860
    Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor regrowth. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by depositing a III-N material, forming an opening in the III-N material, and epitaxially growing within the opening a semiconductor material other than the III-N material. Since the III-N material may serve as a foundation for forming III-N transistors, while the non-III-N material may serve as a foundation for forming non-III-N transistors, such an approach advantageously enables implementation of both types of transistors on a single support structure. Proposed integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.
    Type: Application
    Filed: February 22, 2019
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Johann Christian Rode, Han Wui Then, Marko Radosavljevic, Paul B. Fischer, Nidhi Nidhi, Rahul Ramaswamy, Sandrine Charue-Bakker, Walid M. Hafez
  • Publication number: 20200273839
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.
    Type: Application
    Filed: December 29, 2017
    Publication date: August 27, 2020
    Inventors: Adel A. ELSHERBINI, Henning BRAUNISCH, Aleksandar ALEKSOV, Shawna M. LIFF, Johanna M. SWAN, Patrick MORROW, Kimin JUN, Brennen MUELLER, Paul B. FISCHER
  • Publication number: 20200266190
    Abstract: An integrated circuit die has a layer of first semiconductor material comprising a Group III element and nitrogen and having a first bandgap. A first transistor structure on a first region of the die has: a quantum well (QW) structure that includes at least a portion of the first semiconductor material and a second semiconductor material having a second bandgap smaller than the first bandgap, a first source and a first drain in contact with the QW structure, and a gate structure in contact with the QW structure between the first source and the first drain. A second transistor structure on a second region of the die has a second source and a second drain in contact with a semiconductor body, and a second gate structure in contact with the semiconductor body between the second source and the second drain. The semiconductor body comprises a Group III element and nitrogen.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 20, 2020
    Applicant: INTEL CORPORATION
    Inventors: Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then, Paul B. Fischer, Walid M. Hafez
  • Publication number: 20200266278
    Abstract: A semiconductor device structure having a “T-shaped” gate structure is described. A narrower first portion supports high frequency processes (e.g., gigahertz wireless communications). A second portion of the gate structure has a second width greater than the first width. Lateral extensions (sometimes referred to as “field plates), thinner and wider than the second portion, extend from the second portion. This combination of a gate structure having a narrow first portion and a wider second portion improves the performance of the semiconductor device in applications that involve both high frequency and high power consumption.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 20, 2020
    Applicant: INTEL CORPORATION
    Inventors: Marko RADOSAVLJEVIC, Sansaptak DASGUPTA, Han Wui THEN, Paul B. FISCHER, Walid M. HAFEZ
  • Publication number: 20200235061
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may a die having a front side and a back side, the die comprising a first material and conductive contacts at the front side; and a thermal layer attached to the back side of the die, the thermal layer comprising a second material and a conductive pathway, wherein the conductive pathway extends from a front side of the thermal layer to a back side of the thermal layer.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 23, 2020
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Patrick Morrow, Henning Braunisch, Kimin Jun, Brennen Mueller, Shawna M. Liff, Johanna M. Swan, Paul B. Fischer
  • Patent number: 10720345
    Abstract: Techniques and mechanisms for forming a bond between two wafers. In an embodiment, a first wafer and a second wafer are positioned with respective wafer holders, and are deformed to form a first deformation of the first wafer and a second deformation of the second wafer. The first deformation and the second deformation are symmetrical with respect to a centerline which is between the first wafer and the second wafer. A portion of the first deformation is made to contact, and form a bond with, another portion of the second deformation. The bond is propagated along respective surfaces of the wafers to form a coupling therebetween. In another embodiment, one of the wafer holders comprises one of an array of elements to locally heat or cool a wafer, or an array of displacement stages to locally deform said wafer.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Mauro J. Kobrinsky, Myra McDonnell, Brennen K. Mueller, Chytra Pawashe, Daniel Pantuso, Paul B. Fischer, Lance C. Hibbeler, Martin Weiss
  • Publication number: 20200227407
    Abstract: Disclosed herein are IC structures, packages, and devices that include polysilicon resistors, monolithically integrated on the same substrate/die/chip as III-N transistors. An example IC structure includes an III-N semiconductor material provided over a support structure, a III-N transistor provided over a first portion of the III-N material, and a polysilicon resistor provided over a second portion of the III-N material. Because the III-N transistor and the polysilicon resistor are both provided over a single support structure, they may be referred to as “integrated” transistors. Because the III-N transistor and the polysilicon resistor are provided over different portions of the III-N semiconductor material, and, therefore, over different portion of the support structure, their integration may be referred to as “side-by-side” integration.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Paul B. Fischer, Nidhi Nidhi, Rahul Ramaswamy, Johann Christian Rode, Walid M. Hafez
  • Publication number: 20200227470
    Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same substrate or die as resonators of RF filters. An example IC structure includes a support structure (e.g., a substrate), a resonator, provided over a first portion of the support structure, and an III-N transistor, provided over a second portion of the support structure. The IC structure includes a piezoelectric material so that first and second electrodes of the resonator enclose a first portion of the piezoelectric material, while a second portion of the piezoelectric material is enclosed between the channel material of the III-N transistor and the support structure. In this manner, one or more resonators of an RF filter may be monolithically integrated with one or more III-N transistors. Such integration may reduce costs and improve performance by reducing RF losses incurred when power is routed off chip.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Paul B. Fischer, Zdravko Boos, Marko Radosavljevic, Sansaptak Dasgupta
  • Publication number: 20200227469
    Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same substrate or die as resonators of RF filters. An example IC structure includes a support structure (e.g., a substrate), a resonator, provided over a first portion of the support structure, and an III-N transistor, provided over a second portion of the support structure. The IC structure includes a piezoelectric material so that first and second electrodes of the resonator enclose a first portion of the piezoelectric material, while a second portion of the piezoelectric material is enclosed between the channel material of the III-N transistor and the support structure. In this manner, one or more resonators of an RF filter may be monolithically integrated with one or more III-N transistors. Such integration may reduce costs and improve performance by reducing RF losses incurred when power is routed off chip.
    Type: Application
    Filed: January 16, 2019
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Zdravko Boos, Sansaptak Dasgupta, Marko Radosavljevic, Paul B. Fischer
  • Publication number: 20200227396
    Abstract: The electrical and electrochemical properties of various semiconductors may limit the usefulness of various semiconductor materials for one or more purposes. A completed gallium nitride (GaN) semiconductor layer containing a number of GaN power management integrated circuit (PMIC) dies may be bonded to a completed silicon semiconductor layer containing a number of complementary metal oxide (CMOS) control circuit dies. The completed GaN layer and the completed silicon layer may be full size (e.g., 300 mm). A layer transfer operation may be used to bond the completed GaN layer to the completed silicon layer. The layer transfer operation may be performed on full size wafers. After slicing the full size wafers a large number of multi-layer dies, each having a GaN die layer transferred to a silicon die may be produced.
    Type: Application
    Filed: September 24, 2015
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: Sansaptak W. DASGUPTA, Marko RADOSAVLJEVIC, Han Wui THEN, Ravi PILLARISETTY, Kimin JUN, Patrick MORROW, Valluri R. RAO, Paul B. FISCHER, Robert S. CHAU
  • Publication number: 20200219877
    Abstract: Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N transistors. An example IC structure includes an III-N transistor provided in a first layer over a support structure (e.g., a substrate), and a TFT provided in a second layer over the support structure. The second layer is above the first layer, and, therefore, the III-N transistor and the TFT are “stacked” transistors. This way, one or more III-N transistors may be integrated with one or more TFTs, enabling monolithic integration of PMOS transistors, provided by TFTs, on a single chip with III-N NMOS transistors. Such integration may reduce costs and improve performance, e.g., by reducing RF losses incurred when power is routed off chip in a multi-chip package. Stacked arrangement of III-N transistors and TFTs provides a further advantage of reducing the total surface area occupied by these transistors.
    Type: Application
    Filed: January 9, 2019
    Publication date: July 9, 2020
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Walid M. Hafez
  • Publication number: 20200219878
    Abstract: Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N transistors. An example IC structure includes an III-N semiconductor material provided over a support structure, a III-N transistor provided over a first portion of the III-N material, and a TFT provided over a second portion of the III-N material. Because the III-N transistor and the TFT are both provided over a single support structure, they may be referred to as “integrated” transistors. Because the III-N transistor and the TFT are provided over different portions of the III-N semiconductor material, and, therefore, over different portion of the support structure, their integration may be referred to as “side-by-side” integration. Integrating TFTs with III-N transistors may reduce costs and improve performance, e.g., by reducing losses incurred when power is routed off chip in a multi-chip package.
    Type: Application
    Filed: January 9, 2019
    Publication date: July 9, 2020
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Walid M. Hafez