Patents by Inventor Paul B. Fischer

Paul B. Fischer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200219986
    Abstract: Disclosed herein are IC structures, packages, and devices assemblies that use ions or fixed charge to create field plate structures which are embedded in a dielectric material between gate and drain electrodes of a transistor, ion- or fixed charge-based field plate structures may provide viable approaches to changing the distribution of electric field at a transistor drain to increase the breakdown voltage of a transistor without incurring the large parasitic capacitances associated with the use of metal field plates. In one aspect, an IC structure includes a transistor, a dielectric material between gate and drain electrodes of the transistor, and an ion- or fixed charge-based region within the dielectric material, between the gate and the drain electrodes. Such an ion- or fixed charge-based region realizes an ion- or fixed charge-based field plate structure. Optionally, the IC structure may include multiple ion- or fixed charge-based field plate structures.
    Type: Application
    Filed: January 8, 2019
    Publication date: July 9, 2020
    Applicant: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Glenn A. Glass, Sansaptak Dasgupta, Nidhi Nidhi, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
  • Publication number: 20200212211
    Abstract: A device including a III-N material is described. The device includes a transistor structure having a first layer including a first group III-nitride (III-N) material, a polarization charge inducing layer above the first layer, the polarization charge inducing layer including a second III-N material, a gate electrode above the polarization charge inducing layer and a source structure and a drain structure on opposite sides of the gate electrode. The device further includes a plurality of peripheral structures adjacent to transistor structure, where each of the peripheral structure includes the first layer, but lacks the polarization charge inducing layer, an insulating layer above the peripheral structure and the transistor structure, wherein the insulating layer includes a first dielectric material. A metallization structure, above the peripheral structure, is coupled to the transistor structure.
    Type: Application
    Filed: September 30, 2017
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Marko Radosavljevic, Sansaptak Dasgupta, Han Wui Then, Ibrahim Ban, Paul B. Fischer
  • Publication number: 20200203484
    Abstract: A transistor is disclosed. The transistor includes a substrate, a superlattice structure that includes a plurality of heterojunction channels, and a gate that extends to one of the plurality of heterojunction channels. The transistor also includes a source adjacent a first side of the superlattice structure and a drain adjacent a second side of the superlattice structure.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Nidhi NIDHI, Rahul RAMASWAMY, Sansaptak DASGUPTA, Han Wui THEN, Marko RADOSAVLJEVIC, Johann C. RODE, Paul B. FISCHER, Walid M. HAFEZ
  • Patent number: 10672884
    Abstract: Techniques are disclosed for forming Schottky diodes on semipolar planes of group III-nitride (III-N) material structures. A lateral epitaxial overgrowth (LEO) scheme may be used to form the group III-N material structures upon which Schottky diodes can then be formed. The LEO scheme for forming III-N structures may include forming shallow trench isolation (STI) material on a semiconductor substrate, patterning openings in the STI, and growing the III-N material on the semiconductor substrate to form structures that extend through and above the STI openings, for example. A III-N structure may be formed using only a single STI opening, where such a III-N structure may have a triangular prism-like shape above the top plane of the STI layer. Further processing can include forming the gate (e.g., Schottky gate) and tied together source/drain regions on semipolar planes (or sidewalls) of the III-N structure to form a two terminal Schottky diode.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: June 2, 2020
    Assignee: INTEL CORPORATION
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Paul B. Fischer
  • Patent number: 10673405
    Abstract: Techniques are disclosed for forming high frequency film bulk acoustic resonator (FBAR) devices that include a bottom electrode formed of a two-dimensional electron gas (2DEG). The disclosed FBAR devices may be implemented with various group III-nitride (III-N) materials, and in some cases, the 2DEG may be formed at a heterojunction of two epitaxial layers each formed of III-N materials, such as a gallium nitride (GaN) layer and an aluminum nitride (AlN) layer. The 2DEG bottom electrode may be able to achieve similar or increased carrier transport as compared to an FBAR device having a bottom electrode formed of metal. Additionally, in some embodiments where AlN is used as the piezoelectric material for the FBAR device, the AlN may be epitaxially grown which may provide increased performance as compared to piezoelectric material that is deposited by traditional sputtering techniques.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 2, 2020
    Assignee: INTEL CORPORATION
    Inventors: Sansaptak Dasgupta, Marko Radosavljevic, Han Wui Then, Bruce A. Block, Paul B. Fischer
  • Patent number: 10658475
    Abstract: Integrated circuit transistor structures are provided that may reduce capacitive parasitics by using metal on both sides (top and bottom) of a given integrated circuit transistor device layer. For example, in an embodiment, the drain metal interconnect is provided above the transistor device layer, and the source metal interconnect is provided below the transistor layer. Such a configuration reduces the parasitic capacitance not only between the source and drain metal interconnect layers, but also between the neighboring conductors of the drain metal interconnect layer, because the number of pass-thru conductors in the drain metal interconnect layer to access an upper conductor in the source metal interconnect layer is reduced. In other embodiments, the source metal interconnect remains above the transistor device layer, and the drain metal interconnect is moved to below the transistor device layer, to provide similar benefits. Techniques apply equally to any transistor type, including FETs and BJTs.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 19, 2020
    Assignee: INTEL CORPORATION
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Paul B. Fischer
  • Publication number: 20200144369
    Abstract: Disclosed herein are integrated circuit (IC) components with substrate cavities, as well as related techniques and assemblies. In some embodiments, an IC component may include a substrate, a device layer on the substrate, a plurality of interconnect layers on the device layer, and a cavity in the substrate.
    Type: Application
    Filed: August 9, 2017
    Publication date: May 7, 2020
    Applicant: Intel Corporation
    Inventors: Kevin L. Lin, Paul B. Fischer, Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic, Ibrahim Ban
  • Publication number: 20200135865
    Abstract: A semiconductor device is proposed. The semiconductor device includes a group III-N semiconductor layer, an electrically insulating material layer located on the group III-N semiconductor layer, and a metal contact structure located on the electrically insulating material layer. An electrical resistance between the metal contact structure and the group III-N semiconductor layer through the electrically insulating material layer is smaller than 1*10?7? for an area of 1 mm2. Further, semiconductor devices including a low resistance contact structure, radio frequency devices, and methods for forming semiconductor devices are proposed.
    Type: Application
    Filed: October 24, 2018
    Publication date: April 30, 2020
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta, Paul B. Fischer, Walid M. Hafez
  • Patent number: 10627427
    Abstract: Embodiments relate to the formation of test probes. One method includes providing a bulk sheet of an electrically conductive material. A laser is used to cut through the bulk sheet in a predetermined pattern to form a test probe. Other embodiments are described and claimed.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: April 21, 2020
    Assignee: INTEL CORPORATION
    Inventors: Roy E. Swart, Paul B. Fischer, Charlotte C. Kwong
  • Publication number: 20200119087
    Abstract: Techniques are disclosed for monolithic co-integration of thin-film bulk acoustic resonator (TFBAR, also called FBAR) devices and III-N semiconductor transistor devices. In accordance with some embodiments, one or more TFBAR devices including a polycrystalline layer of a piezoelectric III-N semiconductor material may be formed alongside one or more III-N semiconductor transistor devices including a monocrystalline layer of III-N semiconductor material, over a commonly shared semiconductor substrate. In some embodiments, either (or both) the monocrystalline and the polycrystalline layers may include gallium nitride (GaN), for example. In accordance with some embodiments, the monocrystalline and polycrystalline layers may be formed simultaneously over the shared substrate, for instance, via an epitaxial or other suitable process. This simultaneous formation may simplify the overall fabrication process, realizing cost and time savings, at least in some instances.
    Type: Application
    Filed: July 1, 2016
    Publication date: April 16, 2020
    Applicant: INTEL CORPORATION
    Inventors: HAN WUI THEN, MARKO RADOSAVLJEVIC, SANSAPTAK DASGUPTA, PAUL B. FISCHER, SANAZ K. GARDNER, BRUCE A. BLOCK
  • Publication number: 20200119255
    Abstract: Techniques are disclosed for co-integrating thin-film bulk acoustic resonator (TFBAR, also called FBAR) devices and III-N semiconductor transistor devices. In accordance with some embodiments, a given TFBAR device may include a superlattice structure comprising alternating layers of an epitaxial piezoelectric material, such as aluminum nitride (AlN), and any one, or combination, of other III-N semiconductor materials. For instance, aluminum indium nitride (AlxIn1-xN), aluminum gallium nitride (AlxGa1-xN), or aluminum indium gallium nitride (AlxInyGa1-x-yN) may be interleaved with the AlN, and the particular compositional ratios thereof may be adjusted to customize resonator performance. In accordance with some embodiments, the superlattice layers may be formed via an epitaxial deposition process, allowing for precise control over film thicknesses, in some cases in the range of a few nanometers.
    Type: Application
    Filed: July 1, 2016
    Publication date: April 16, 2020
    Applicant: INTEL CORPORATION
    Inventors: HAN WUI THEN, SANSAPTAK DASGUPTA, MARKO RADOSAVLJEVIC, PAUL B. FISCHER
  • Publication number: 20200066848
    Abstract: An apparatus including a transistor device on a substrate including an intrinsic layer including a channel; a source and a drain on opposite sides of the channel; and a diffusion barrier between the intrinsic layer and each of the source and the drain, the diffusion barrier including a conduction band energy that is less than a conduction band energy of the channel and greater than a material of the source and drain. A method including defining an area of an intrinsic layer on a substrate for a channel of a transistor device; forming a diffusion barrier layer in an area defined for a source and a drain; and forming a source on the diffusion barrier layer in the area defined for the source and forming a drain in the area defined for the drain.
    Type: Application
    Filed: April 1, 2016
    Publication date: February 27, 2020
    Inventors: Han Wui THEN, Sansaptak DASGUPTA, Marko RADOSAVLJEVIC, Paul B. FISCHER
  • Patent number: 10573715
    Abstract: Embodiments of the present disclosure describe techniques for backside isolation for devices of an integrated circuit (IC) and associated configurations. The IC may include a plurality of devices (e.g., transistors) formed on a semiconductor substrate. The semiconductor substrate may include substrate regions on which one or more devices are formed. Trenches may be disposed between the devices on the semiconductor substrate. Portions of the semiconductor substrate between the substrate regions may be removed to expose the corresponding trenches and form isolation regions. An insulating material may be formed in the isolation regions. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Rishabh Mehandru, Harold W. Kennel, Paul B. Fischer, Stephen M. Cea
  • Publication number: 20200043917
    Abstract: Enhancement/depletion device pairs and methods of producing the same are disclosed. A disclosed example multilayered die includes a depletion mode device that includes a first polarization layer and a voltage tuning layer, and an enhancement mode device adjacent the depletion mode device, where the enhancement mode device includes a second polarization layer, and where the second polarization layer includes an opening corresponding to a gate of the enhancement mode device.
    Type: Application
    Filed: March 31, 2017
    Publication date: February 6, 2020
    Applicant: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Paul B. Fischer
  • Patent number: 10529827
    Abstract: Embodiments of the invention include vertically oriented long channel transistors and methods of forming such transistors. In one embodiment, a method of forming such a transistor may include forming a fin on a semiconductor substrate. Embodiments may also include forming a spacer over an upper portion of the fin and a lower portion of the fin not covered by the spacer may be exposed. Embodiments may also include forming a gate dielectric layer over the exposed portion of the fin. A gate electrode may then be deposited, according to an embodiment. Embodiments may include exposing a top portion of the fin and forming a first source/drain (S/D) region in the top portion of the fin. The second S/D region may be formed by removing the semiconductor substrate to expose a bottom portion of the fin and forming the second S/D region in the bottom portion of the fin.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 7, 2020
    Assignee: Intel Corporation
    Inventors: Rishabh Mehandru, Patrick Morrow, Paul B. Fischer, Aaron D. Lilak, Stephen M. Cea
  • Patent number: 10522510
    Abstract: A method including coupling a device substrate to a carrier substrate; aligning a portion of the device substrate to a host substrate; separating the portion of the device substrate from the carrier substrate; and after separating the portion of the device substrate, coupling the portion of the device substrate to the host substrate. A method including coupling a device substrate to a carrier substrate with an adhesive between a device side of the device substrate and the carrier substrate; after coupling the device substrate to the carrier substrate, thinning the device substrate; aligning a portion of the thinned device substrate to a host substrate; separating the portion of the device substrate from the carrier substrate; and coupling the separated portion of the device substrate to the host substrate. An apparatus including a substrate including a submicron thickness and a device layer coupled to a host substrate in a stacked arrangement.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventors: Kimin Jun, Jacob M. Jensen, Patrick Morrow, Paul B. Fischer
  • Publication number: 20190371743
    Abstract: A guard ring structure includes a ring of semiconductor material disposed on a substrate. A conductive ring is disposed on the ring of semiconductor material. The conductive ring is interconnected by intervening vias. The guard ring structure may include a plurality of individual rings of the semiconductor material formed concentrically and in close proximity to one another on the substrate. A Guard ring structure is generally disposed around a periphery of a die containing integrated circuits that include transistors RF amplifiers and memory devices to reduce the impact of stresses arising from die sawing to separate individual die in a wafer.
    Type: Application
    Filed: December 30, 2016
    Publication date: December 5, 2019
    Inventors: Han Wui THEN, Marko RADOSAVLJEVIC, Sansaptak DASGUPTA, Paul B. FISCHER
  • Publication number: 20190371666
    Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: August 13, 2019
    Publication date: December 5, 2019
    Inventors: Il-Seok SON, Colin T. CARVER, Paul B. FISCHER, Patrick MORROW, Kimin JUN
  • Patent number: 10490449
    Abstract: Embodiments of the present disclosure describe techniques for revealing a backside of an integrated circuit (IC) device, and associated configurations. The IC device may include a plurality of fins formed on a semiconductor substrate (e.g., silicon substrate), and an isolation oxide may be disposed between the fins along the backside of the IC device. A portion of the semiconductor substrate may be removed to leave a remaining portion. The remaining portion may be removed by chemical mechanical planarization (CMP) using a selective slurry to reveal the backside of the IC device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: November 26, 2019
    Assignee: Intel Corporation
    Inventors: Il-Seok Son, Colin T. Carver, Paul B. Fischer, Patrick Morrow, Kimin Jun
  • Publication number: 20190333906
    Abstract: An apparatus is provided which comprises: a substrate; a first active device adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; a second active device coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first set and the second active device, wherein the layer is to bond the one of the layers of the first set and the second active device.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 31, 2019
    Applicant: Intel Corporation
    Inventors: Anup Pancholi, Prashant Majhi, Paul B. Fischer, Patrick Morrow