Patents by Inventor Paul B. Fischer

Paul B. Fischer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140117559
    Abstract: Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate (ZrW2O8) or hafnium tungstate (HfW2O8). In some cases, the NTE material is disposed between the substrate and conductive core material of the TSV and serves to offset, at least in part, the coefficient of thermal expansion (CTE) mismatch there between, thus reducing heat-induced stresses and/or protrusion (pumping) of the conductive core material. The NTE material also may protect against leakage, voltage breakdown, and/or diffusion of the conductive core material. Furthermore, the NTE material may reduce radial stresses in high-aspect-ratio TSVs. In some cases, techniques disclosed herein may improve TSV reliability, enhance three-dimensional integration, and/or enhance performance in three-dimensional integrated circuits and/or other three-dimensional packages.
    Type: Application
    Filed: March 30, 2012
    Publication date: May 1, 2014
    Inventors: Paul A. Zimmerman, Scott B. Clendenning, Patricio E. Romero, Paul B. Fischer, Robert Edgeworth
  • Publication number: 20140106560
    Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.
    Type: Application
    Filed: December 18, 2013
    Publication date: April 17, 2014
    Inventors: Qing Ma, Jun He, Patrick Morrow, Paul B. Fischer, Sridhar Balakrishnan, Satish Radhakrishnan, Tatyana Tanya Andryushcheko, Guanghai Xu
  • Publication number: 20140092574
    Abstract: Magnetically enhanced inductors integrated with microelectronic devices at chip-level. In embodiments, magnetically enhanced inductors include a through substrate vias (TSVs) with fill metal to carry an electrical current proximate to a magnetic layer disposed on a substrate through which the TSV passes. In certain magnetically enhanced inductor embodiments, a TSV fill metal is disposed within a magnetic material lining the TSV. In certain magnetically enhanced inductor embodiments, a magnetically enhanced inductor includes a plurality of interconnected TSVs disposed proximate to a magnetic material layer on a side of a substrate. In embodiments, voltage regulation circuitry disposed on a first side of a substrate is integrated with one or more magnetically enhanced inductors utilizing a TSV passing through the substrate.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Uwe ZILLMANN, Andre SCHAEFER, Ruchir SARASWAT, Telesphor KAMGAING, Paul B. FISCHER, Guido DROEGE
  • Publication number: 20140029150
    Abstract: An interposer is described to regulate the current in wafer test tooling. In one example, the interposer includes a first connection pad to couple to automated test equipment and a second connection pad to couple to a device under test. The interposer further includes an overcurrent limit circuit to connect the first and second connection pads and to disconnect the first and second connection pads when the current between the first and second connection pads is over a predetermined amount.
    Type: Application
    Filed: March 6, 2012
    Publication date: January 30, 2014
    Inventors: Evan M. Fledell, Paul B. Fischer, Roy E. Swart, Timothy J. Maloney, Jack D. Pippin
  • Patent number: 8637778
    Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: January 28, 2014
    Assignee: Intel Corporation
    Inventors: Qing Ma, Jun He, Patrick Morrow, Paul B. Fischer, Sridhar Balakrishnan, Satish Radhakrishnan, Tatyana Tanya Andryushchenko, Guanghai Xu
  • Patent number: 8513966
    Abstract: Embodiments of the invention describe forming a set of probes using semiconductor regions each including a plurality of vias. A first set of probe segments may be formed from a first set of vias on a first semiconductor region. A second set of probe segments may be formed from a second set of vias on a second semiconductor region and bonded to the first set of probe segments. At least one spring comprising a dielectric material may be formed to couple the first set of probe segments, while a set of metal tips disposed on the second set of probe segments.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: August 20, 2013
    Assignee: Intel Corporation
    Inventors: Qing Ma, Roy E. Swart, Paul B. Fischer, Johanna M. Swan
  • Publication number: 20130000117
    Abstract: Embodiments of the invention provide methods for forming electrical connections using liquid metals. Electrical connections that employ liquid metals are useful for testing and validation of semiconductor devices. Electrical connections are formed between the probes of a testing interface and the electronic interface of a device under test through a liquid metal region. In embodiments of the invention, liquid metal interconnects are comprised of gallium or liquid metal alloys of gallium. The use of liquid metal contacts does not require a predetermined amount of force be applied in order to reliably make an electrical connection.
    Type: Application
    Filed: June 30, 2011
    Publication date: January 3, 2013
    Inventors: Rajashree Baskaran, Kimin Jun, Ting Zhong, Roy E. Swart, Paul B. Fischer
  • Publication number: 20120038379
    Abstract: Embodiments of the invention describe forming a set of probes using semiconductor regions each including a plurality of vias. A first set of probe segments may be formed from a first set of vias on a first semiconductor region. A second set of probe segments may be formed from a second set of vias on a second semiconductor region and bonded to the first set of probe segments. At least one spring comprising a dielectric material may be formed to couple the first set of probe segments, while a set of metal tips disposed on the second set of probe segments.
    Type: Application
    Filed: August 11, 2010
    Publication date: February 16, 2012
    Inventors: Qing Ma, Roy E. Swart, Paul B. Fischer, Johanna M. Swan
  • Publication number: 20110247872
    Abstract: The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress.
    Type: Application
    Filed: April 8, 2010
    Publication date: October 13, 2011
    Inventors: Qing Ma, Jun He, Patrick Morrow, Paul B. Fischer, Sridhar Balakrishnan, Satish Radhakrishnan, Tatyana Tanya Andryushchenko, Guanghai Xu
  • Patent number: 7666465
    Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include providing a substrate comprising at least one opening, and then applying a nanotube slurry comprising at least one nanotube to the substrate, wherein the at least one nanotube is substantially placed within the at least one opening.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: February 23, 2010
    Assignee: Intel Corporation
    Inventors: Paul B. Fischer, Anne E. Miller, Kenneth C. Cadien, Chris E. Barns
  • Patent number: 7205236
    Abstract: According to one aspect of the present invention, a method of electrochemically polishing a semiconductor substrate may be provided. A semiconductor substrate processing fluid, having a plurality of abrasive particles therein, may be placed between the surface of the semiconductor substrate and the polish head. The polish head may be moved relative to the surface of the semiconductor substrate to cause the abrasive particles to polish the surface of the semiconductor substrate. According to a second aspect of the present invention, a method for electro-polishing a semiconductor substrate may be provided. A semiconductor substrate may be placed in an electrolytic solution. A surface of the semiconductor substrate may be contacted with at least one conductive member. A voltage may be applied across the electrolytic solution and the at least one conductive member. The at least one conductive member may be moved across the surface of the semiconductor substrate.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: April 17, 2007
    Assignee: Intel Corporation
    Inventors: Paul B. Fischer, Chris E. Barns
  • Patent number: 7105925
    Abstract: Method and structure for optimizing and controlling chemical mechanical planarization are disclosed. Embodiments of the invention include planarization techniques to make nonplanar surfaces comprising alternating metal and intermetal layers. Relative protrusion dimensions and uniformity of various layers may be accurately controlled using the disclosed techniques.
    Type: Grant
    Filed: February 2, 2005
    Date of Patent: September 12, 2006
    Assignee: Intel Corporation
    Inventors: James A. Boardman, Sarah E. Kim, Paul B. Fischer, Mauro J. Kobrinsky
  • Patent number: 6914002
    Abstract: Method and structure for optimizing and controlling chemical mechanical planarization are disclosed. Embodiments of the invention include planarization techniques to make nonplanar surfaces comprising alternating metal and intermetal layers. Relative protrusion dimensions and uniformity of various layers may be accurately controlled using the disclosed techniques.
    Type: Grant
    Filed: December 28, 2002
    Date of Patent: July 5, 2005
    Assignee: Intel Corporation
    Inventors: James A. Boardman, Sarah E. Kim, Paul B. Fischer, Mauro J. Kobrinsky
  • Publication number: 20040127049
    Abstract: Method and structure for optimizing and controlling chemical mechanical planarization are disclosed. Embodiments of the invention include planarization techniques to make nonplanar surfaces comprising alternating metal and intermetal layers. Relative protrusion dimensions and uniformity of various layers may be accurately controlled using the disclosed techniques.
    Type: Application
    Filed: December 28, 2002
    Publication date: July 1, 2004
    Inventors: James A. Boardman, Sarah E. Kim, Paul B. Fischer, Mauro J. Kobrinsky
  • Patent number: 5595526
    Abstract: A method for polishing the surface of a substrate that overcomes the problems inherent in the prior art. During the polishing of a substrate, a quantity is calculated which is approximately proportional to a share of the total energy the polisher is consuming. Once this calculated quantity reaches a predetermined amount, it is detected.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: January 21, 1997
    Assignee: Intel Corporation
    Inventors: Leopoldo D. Yau, Paul B. Fischer