Patents by Inventor Paul Brazis

Paul Brazis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9441384
    Abstract: Aspects of this invention relate to a barrier for fixing to an portion of a wall. The barrier includes at least one plate that is securable to the wall. For each plate, there is a vertical upright attached to and extending upwardly from the plate to which the barrier is secured. The barrier is held by the vertical upright above the upper portion of the wall as required. removable from the vertical upright to allow access to the upper portion of the wall as required. In one aspect, at least a portion of the barrier is moveable relative to a remainder of the barrier and between a first portion, where it is located above an upper edge of the wall, and a second portion, where access is then provided to the upper wall edge above which the movable barrier portion was positioned.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: September 13, 2016
    Assignee: Form 700 Pty Ltd
    Inventors: Emilio Rosati, Paul Brazis
  • Publication number: 20130037770
    Abstract: This invention relates to a barrier for fixing to an upper portion of a wall, the barrier comprising fixing means securable to the wall, and a barrier held by the fixing means that locates above the upper portion of the wall, wherein the barrier is removable from the fixing means to allow access to the upper portion of the wall as required. In one aspect, at least a portion of the barrier is moveable relative to a remainder of the barrier and between a first position where it is located above an upper edge of the wall, and a second position where access is then provided to the upper wall edge above which the movable barrier portion was previously positioned.
    Type: Application
    Filed: February 24, 2011
    Publication date: February 14, 2013
    Applicant: Form 700 Pty Ltd
    Inventors: Emilio Rosati, Paul Brazis
  • Publication number: 20070247824
    Abstract: An electronic apparatus, includes a plurality of electronic modules, each having a maximum thickness of no more than 90 microns, each comprising a substrate having a two sided edge connection pattern. The electronic modules are arranged adjacent to each other. Each pad of a first set of connection pads on a first electronic module is conductively connected to an opposing pad of a second set of connection pads of a second electronic module. The first set of connection pads is separated from the second set of connection pads by electrically conductive material that is less than 15 microns thick.
    Type: Application
    Filed: April 21, 2006
    Publication date: October 25, 2007
    Applicant: MOTOROLA, INC.
    Inventors: Paul Brazis, Marc Chason, Daniel Gamota, Krishna Kalyanasundaram
  • Publication number: 20070094624
    Abstract: An apparatus (200) such as a semiconductor device comprises a gate electrode (201) and at least a first electrode (202). The first electrode preferably has an established perimeter that at least partially overlaps with respect to the gate electrode to thereby form a corresponding transistor channel. In a preferred approach the first electrode has a surface area that is reduced notwithstanding the aforementioned established perimeter. This, in turn, aids in reducing any corresponding parasitic capacitance. This reduction in surface area may be accomplished, for example, by providing openings (203) through certain portions of the first electrode.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 26, 2007
    Inventors: Paul Brazis, Daniel Gamota, Krishna Kalyanasundaram, Jie Zhang
  • Publication number: 20070090869
    Abstract: A power source (201) and a printed transistor circuit (202) are combined with one another in a stacked and integral configuration. In a preferred though optional configuration this combination can further comprise a substrate (200) of choice. The power source can comprise a technology of choice such as, but not limited, to, a battery or a photovoltaic element. These elements can be combined (104) using a joining technology of choice such as, but not limited to, laminating these elements together or printing one upon the other.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 26, 2007
    Inventors: Hakeem Adewole, Paul Brazis, Gabriela Dyrc, Daniel Gamota, Jie Zhang
  • Publication number: 20070090950
    Abstract: An object (201) (such as a containment mechanism) supports both a functional electrical circuit (203) and an electrical circuit (202) to which the functional electrical circuit is responsive. In a preferred approach the functional electrical circuit has both a low power state of operation and a higher power state of operation. Upon detecting (104) that an area of connectivity of the electrical circuit has been severed (via, for example, corresponding manipulation of the object itself), the functional electrical circuit responsively operates (106) using the higher power state of operation.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 26, 2007
    Inventors: Mansour Toloo, Hakeem Adewole, Paul Brazis, Daniel Gamota, Julius Gyorfi, Swee Mok, John Szczech, Jie Zhang
  • Publication number: 20070089540
    Abstract: A printing platform receives (102) (preferably in-line with a semiconductor device printing process (101)) a substrate having at least one semiconductor device printed thereon and further having a test structure printed thereon, which test structure comprises at least one printed semiconductor layer. These teachings then provide for the automatic testing (103) of the test structure with respect to at least one static (i.e., relatively unchanging) electrical characteristic metric. The static electrical characteristic metric (or metrics) of choice will likely vary with the application setting but can include, for example, a measure of electrical resistance, a measure of electrical reactance, and/or a measure of electrical continuity. Optionally (though preferably) the semiconductor device printing process itself is then adjusted (105) as a function, at least in part, of this metric.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 26, 2007
    Inventors: Paul Brazis, Daniel Gamota, Krishna Kalyanasundaram, Jie Zhang, Krishna Jonnalagadda
  • Publication number: 20070089626
    Abstract: A functional ink (200) suitable for use as a dielectric layer (303) in a printed semiconductor device (300) comprises a dielectric carrier (201) and a plurality of dielectric particles (202) sized less than about 1,000 nanometers that are disposed within the dielectric carrier. In a preferred approach the dielectric carrier comprises a dielectric resin and the dielectric particles comprise a ferroelectric material (such as, but not limited to, BaTiO3. So provided, this functional ink can be applied to a substrate (301) of choice through a printing technique of choice to thereby provide a resultant printed semiconductor device, such as a field effect transistor, having a relatively thin dielectric layer comprised of this functional ink.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 26, 2007
    Inventors: Amjad Rasul, Paul Brazis, Daniel Gamota, Andrew Skipor, Jie Zhang
  • Publication number: 20070090459
    Abstract: A printed transistor has a first gate (202) printed and disposed on a first side of a printed deposit of semiconductor material (201) and a second printed gate (301) disposed on an opposite side of the printed deposit of semiconductor material. By one approach these elements are provided using a serial printing process. By another approach these elements are provided through use of a lamination process.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 26, 2007
    Inventors: Jie Zhang, Hakeem Adewole, Paul Brazis, Timothy Collins, Daniel Gamota, John Szczech, Jerzy Wielgus
  • Publication number: 20070090858
    Abstract: An inverter circuit (500) having a drive transistor (102) that operably couples to a voltage bias input (101) (and where that drive transistor controls the inverter circuit output by opening and closing a connection between the output (105) and ground (104)) is further operably coupled to a feedback switch (401). In a preferred approach the feedback switch is itself also operably coupled to the voltage bias input and the output and preferably serves, when the drive transistor is switched “off,” to responsively couple the voltage bias input to the drive transistor in such a way as to cause a gate terminal of the drive transistor to have its polarity relative to a source terminal of the drive transistor reversed and hence permit the inverter circuit to operate across a substantially full potential operating range of the drive transistor.
    Type: Application
    Filed: October 26, 2005
    Publication date: April 26, 2007
    Inventors: Paul Brazis, Daniel Gamota, Kin Tsui, John Szczech, Jie Zhang
  • Publication number: 20060131545
    Abstract: The density (and hence thickness) of a functional ink layer (41) as comprises a part of an active printed electronic component (71) is determined through interaction (13) of the functional ink with light. This information, in turn, facilitates assessment (14) of the likely corresponding electrical performance of the electronic component. When the functional ink comprises a transparent material, a dye can be added to facilitate the desired interaction and assessment.
    Type: Application
    Filed: December 16, 2004
    Publication date: June 22, 2006
    Inventors: Krishna Kalyanasundaram, Paul Brazis, Daniel Gamota, Abhijit Chowdhuri, Jie Zhang
  • Publication number: 20060121182
    Abstract: Data regarding printing instructions for an active electronic component are provided (11). These printing instructions will typically comprise instructions regarding the location, geometry, size, orientation, and functional inks used for various component layers as correspond to the electronic component, and are without reference to a specific printing system. This data is then modified (12) as a function of one or more operational proclivities of a particular high throughput additive printing system to provide modified instructions that, when employed to effect the printing of the active electronic component, will improve the resultant yield as compared to the unmodified data.
    Type: Application
    Filed: December 3, 2004
    Publication date: June 8, 2006
    Inventors: Krishna Kalyanasundaram, Paul Brazis, Daniel Gamota, Jie Zhang
  • Publication number: 20060003475
    Abstract: Two or more semiconductor devices (21 and 22) are formed on a substrate (20) and are each comprised of a plurality of printed components (23 and 24). At least one such printed component (25) is shared by both such semiconductor devices.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Hakeem Adewole, Paul Brazis, Daniel Gamota, Jerzy Wielgus, Jie Zhang
  • Publication number: 20060001021
    Abstract: A semiconductor device can be comprised of a substrate having a plurality of different printable semiconductor inks formed thereon. In a preferred approach at least some of these printable semiconductor inks comprise organic semiconductor material inks. These semiconductor inks can vary from one another with respect to various properties including but not limited to electrical characteristics and environmental efficacy.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Hakeem Adewole, Paul Brazis, Daniel Gamota, Jie Zhang
  • Publication number: 20050273552
    Abstract: A method and apparatus for writing to solid-state memory is provided herein. In particular, a controller is provided that monitors operating parameters of each die within the system. In order to enable fast, real-time write operations, feedback from each die is analyzed and compared with a stored set of operating parameters. Based on this comparison, a particular die is chosen for write operations such that system performance is optimized.
    Type: Application
    Filed: August 4, 2005
    Publication date: December 8, 2005
    Inventors: Paul Brazis, Thomas Tirpak, Kin Tsui, Krishna Kalyanasundaram, Daniel Gamota
  • Publication number: 20050189968
    Abstract: An organic semiconductor inverting circuit includes at least three organic transistors, an output terminal (110, 210, 310, 410), a reference supply voltage input (115, 215, 315, 415), a first positive supply voltage input (120, 220, 320, 420), and a negative supply voltage input (125, 225, 325, 425). One of the three organic transistors is an input transistor having a gate to which is coupled an input terminal (105, 205, 305, 405). The output terminal (110, 210, 310, 410) is coupled to a first electrode of at least one of the at least three organic transistors.
    Type: Application
    Filed: February 27, 2004
    Publication date: September 1, 2005
    Inventors: Paul Brazis, Hakeem Adewole, Daniel Gamota, Jie Zhang
  • Publication number: 20050176196
    Abstract: Organic field effect transistors (OFETs) can be created rapidly and at low cost on organic films by using a multilayer film (202) that has an electrically conducting layer (204, 206) on each side of a dielectric core. The electrically conducting layer is patterned to form gate electrodes (214), and a polymer film (223) is attached onto the gate electrode side of the multilayer dielectric film, using heat and pressure (225) or an adhesive layer (228). A source electrode and a drain electrode (236) are then fashioned on the remaining side of the multilayer dielectric film, and an organic semiconductor (247) is deposited over the source and drain electrodes, so as to fill the gap between the source and drain electrodes and touch a portion of the dielectric film to create an organic field effect transistor.
    Type: Application
    Filed: April 8, 2005
    Publication date: August 11, 2005
    Inventors: Jie Zhang, Paul Brazis, Daniel Gamota, Krishna Kalyanasundaram, Min-Xian Zhang
  • Patent number: 6905908
    Abstract: Organic field effect transistors (OFETs) can be created rapidly and at low cost on organic films by using a multilayer film (202) that has an electrically conducting layer (204, 206) on each side of a dielectric core. The electrically conducting layer is patterned to form gate electrodes (214), and a polymer film (223) is attached onto the gate electrode side of the multilayer dielectric film, using heat and pressure (225) or an adhesive layer (228). A source electrode and a drain electrode (236) are then fashioned on the remaining side of the multilayer dielectric film, and an organic semiconductor (247) is deposited over the source and drain electrodes, so as to fill the gap between the source and drain electrodes and touch a portion of the dielectric film to create an organic field effect transistor.
    Type: Grant
    Filed: December 26, 2002
    Date of Patent: June 14, 2005
    Assignee: Motorola, Inc.
    Inventors: Jie Zhang, Daniel Gamota, Min-Xian Zhang, Paul Brazis, Krishna Kalyanasundaram
  • Patent number: 6870181
    Abstract: An organic field effect transistor utilizes a bifunctional contact-enhancing agent at various interfaces to improve carrier mobility through the organic semiconductor layer, to improve carrier injection, and to enhance adhesion via a bifunctional mechanism. The contact-enhancing agent can be situated between the gate electrode (2) and the dielectric layer (3) to form a chemical or physical bond between the gate electrode and the dielectric layer. It can also be situated between the dielectric layer and the organic semiconducting layer (4), or between the source and drain electrodes (5, 6) and the organic semiconducting layer.
    Type: Grant
    Filed: July 2, 2002
    Date of Patent: March 22, 2005
    Assignee: Motorola, Inc.
    Inventors: Jie Zhang, Paul Brazis, Daniel Gamota, Krishna Kalyanasundaram, Steven Scheifers, Jerzy Wielgus, Abhijit Roy Chowdhuri
  • Patent number: 6868352
    Abstract: An organic semiconductor product state monitor attached to a product receives a product usefulness input, which, along with the product predetermined usefulness limit, is used to determine an indicator command to indicate a state of usefulness of the product. An organic circuit is formed and placed on a product with a power supply to control the circuit operation.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: March 15, 2005
    Assignee: Motorola, Inc.
    Inventors: Hakeem Adewole, Paul Brazis, Daniel Gamota, Jie Zhang