Abstract: An integrated circuit having a temperature sensitive circuit (TSC) to generate a signal indicative of the substrate temperature near the TSC. The integrated circuit has circuitry configured to receive a TSC signal from at least one TSC and to convert the TSC signal to a signal indicative of the integrated circuit's temperature. The thermal control circuit compares the integrated circuit temperature to a threshold and produces a corrective action signal when the temperature exceeds the threshold. The corrective action signal is provided to corrective action circuitry preferably configured to modify the operation of the IC to reduce the IC temperature in proximity to the corresponding TSC.

Abstract: An integrated circuit having a temperature sensitive circuit (TSC) to generate a signal indicative of the substrate temperature near the TSC. The integrated circuit has circuitry configured to receive a TSC signal from at least one TSC and to convert the TSC signal to a signal indicative of the integrated circuit's temperature. The thermal control circuit compares the integrated circuit temperature to a threshold and produces a corrective action signal when the temperature exceeds the threshold. The corrective action signal is provided to corrective action circuitry preferably configured to modify the operation of the IC to reduce the IC temperature in proximity to the corresponding TSC.

Abstract: A system for improving system cycle time while supporting 1½ cycle data paths with a PLL based clock system using a communication circuit providing a first mode of operation whereby a first cycle time is obtained, and for allowing use of a second mode of operation whereby a second longer multi-mode cycle time is obtained to extend the time for evaluation of data on the bi-directional data path between a first chip and a memory circuit.

Abstract: A reduction of multichip module computer system cycle time is achieved by using a voltage regulator for power supply noise attenuation to reduce jitter. The circuit for doing this includes an active filter network circuit for use in the multichip module of a computer system which generates a quiet analog VDD coupled directly to ground by using the low impedance power supply distributions which already exist in the module. The active filter network permits taking the power supply voltage from the module and stepping it down to a voltage needed by a phased lock loop via an active filter, said active filter comprising an op-amplifier and a source follower and a large value on module capacitor for a resistor network. The capacitor and resistor network acts as a filter with a large time constant where noise appearing on VDD,MOD is completely attenuated by this high value capacitor and resistor network part of our active filter network.

Abstract: A lock circuit for indicating a locked/unlocked condition of phased lock loops circuits, which uses a reference clock signal input to a good-cycle counter and to a bad-cycle counter to signal a set/reset latch to output a signal indicating whether or not the phase of the output signal and input clock are in phase. Phase detector inputs are XOR gated to produce a pulse when the phase locked output clock is in a bad cycle indicated by the phase locked output clock not being in-phase with its input clock. Pulses on the XOR gate output on a bad cycle feed a single cycle counter reset circuit. The single cycle counter reset circuit on every cycle resets one of the bad and good counters based on its detection of a bad cycle pulse from the XOR gate. The good-cycle counter's output is to the SET input of the set/reset latch, and the bad-cycle counter's output is to the RESET input of the set/reset latch . We enable specific cycling of both the good and bad counters.