Patents by Inventor Paul Demone

Paul Demone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8587280
    Abstract: A power supply arrangement includes a PFC converter, an LLC converter, a control unit and an offset unit. The control unit generates a control signal to control a duty cycle of a PWM (Pulse Width Modulation) signal to control the PFC converter. The control unit includes a PWM converter that generates the PWM signal to which a switching circuit is responsive to switch a current representing an input current of the PFC converter. An amplifier receives a current sense signal and provides the current representing the input current of the PFC converter. An offset unit generates a variable offset signal to offset the control signal or a signal used by the control unit to generate the control signal. The variable offset signal is an offset current coupled to offset the current sense signal received at the input of the amplifier.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: November 19, 2013
    Assignee: Power Integrations, Inc.
    Inventors: Roger Colbeck, Paul DeMone, Anthony Peter Ernest Reinberger
  • Patent number: 8582319
    Abstract: A resonant mode converter includes a PFC power converter having an input coupled to receive an input voltage. An LLC power converter is cascaded with the PFC power converter. The LLC power converter includes a transformer coupled to generate an output of the resonant mode converter. A feedback circuit is coupled to generate a first current representative of the output of the resonant mode converter. A control unit includes a current limiting circuit coupled to receive the first current and a second current generated in response to a reference voltage. The current limiting circuit is coupled to limit the first current in response to the second current. The control unit further includes an oscillator coupled to generate a control signal having a control frequency in response to the first current. The resonant mode converter output is controlled in response to the control frequency.
    Type: Grant
    Filed: August 22, 2012
    Date of Patent: November 12, 2013
    Assignee: Power Integrations, Inc.
    Inventors: Anthony Reinberger, Paul Demone
  • Patent number: 8503250
    Abstract: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: August 6, 2013
    Assignee: MOSAID Technologies Incorporated
    Inventor: Paul Demone
  • Publication number: 20120314457
    Abstract: A resonant mode converter includes a PFC power converter having an input coupled to receive an input voltage. An LLC power converter is cascaded with the PFC power converter. The LLC power converter includes a transformer coupled to generate an output of the resonant mode converter. A feedback circuit is coupled to generate a first current representative of the output of the resonant mode converter. A control unit includes a current limiting circuit coupled to receive the first current and a second current generated in response to a reference voltage. The current limiting circuit is coupled to limit the first current in response to the second current. The control unit further includes an oscillator coupled to generate a control signal having a control frequency in response to the first current. The resonant mode converter output is controlled in response to the control frequency.
    Type: Application
    Filed: August 22, 2012
    Publication date: December 13, 2012
    Applicant: POWER INTEGRATIONS, INC.
    Inventors: Anthony Reinberger, Paul Demone
  • Publication number: 20120274298
    Abstract: A power supply arrangement includes a PFC converter, an LLC converter, a control unit and an offset unit. The control unit generates a control signal to control a duty cycle of a PWM (Pulse Width Modulation) signal to control the PFC converter. The control unit includes a PWM converter that generates the PWM signal to which a switching circuit is responsive to switch a current representing an input current of the PFC converter. An amplifier receives a current sense signal and provides the current representing the input current of the PFC converter. An offset unit generates a variable offset signal to offset the control signal or a signal used by the control unit to generate the control signal. The variable offset signal is an offset current coupled to offset the current sense signal received at the input of the amplifier.
    Type: Application
    Filed: July 11, 2012
    Publication date: November 1, 2012
    Applicant: POWER INTEGRATIONS, INC.
    Inventors: Roger Colbeck, Paul DeMone, Anthony Peter Ernest Reinberger
  • Patent number: 8274799
    Abstract: A resonant mode power converter is controlled with a control unit including a current limiting circuit coupled to receive a first current representative of a power converter output and a second current generated in response to a reference voltage. The current limiting circuit is coupled to limit the first current in response to the second current. An oscillator is coupled to receive the first current to generate a control signal having a control frequency in response to the first current. The power converter output is controlled in response to the control frequency of the control signal.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: September 25, 2012
    Assignee: Power Integrations, Inc.
    Inventors: Anthony Reinberger, Paul Demone
  • Patent number: 8248051
    Abstract: An apparatus includes a control unit to generate a control signal to control a duty cycle of a PWM switching signal that controls a switch in a PFC converter. The control unit includes a PWM converter to produce a PWM signal responsive to an output voltage of the PFC converter. A switching circuit switches a current representing an input current of the PFC converter in response to the PWM signal. A circuit generates the control signal in response to the switched current. The control unit includes an amplifier that receives a current sense signal and provides the current representing the input current of the PFC converter. An offset unit generates a variable offset signal to generate the control signal. The offset unit provides the offset signal as an offset current for offsetting a current at an input of the amplifier.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: August 21, 2012
    Assignee: Power Integrations, Inc.
    Inventors: Roger Colbeck, Paul DeMone, Anthony Peter Ernest Reinberger
  • Publication number: 20120091982
    Abstract: An apparatus includes a control unit to generate a control signal to control a duty cycle of a PWM switching signal that controls a switch in a PFC converter. The control unit includes a PWM converter to produce a PWM signal responsive to an output voltage of the PFC converter. A switching circuit switches a current representing an input current of the PFC converter in response to the PWM signal. A circuit generates the control signal in response to the switched current. The control unit includes an amplifier that receives a current sense signal and provides the current representing the input current of the PFC converter. An offset unit generates a variable offset signal to generate the control signal. The offset unit provides the offset signal as an offset current for offsetting a current at an input of the amplifier.
    Type: Application
    Filed: December 21, 2011
    Publication date: April 19, 2012
    Applicant: POWER INTEGRATIONS, INC.
    Inventors: Roger Colbeck, Paul DeMone, Anthony Peter Ernest Reinberger
  • Publication number: 20120057372
    Abstract: A resonant mode power converter is controlled with a control unit including a current limiting circuit coupled to receive a first current representative of a power converter output and a second current generated in response to a reference voltage. The current limiting circuit is coupled to limit the first current in response to the second current. An oscillator is coupled to receive the first current to generate a control signal having a control frequency in response to the first current. The power converter output is controlled in response to the control frequency of the control signal.
    Type: Application
    Filed: August 4, 2011
    Publication date: March 8, 2012
    Applicant: POWER INTEGRATIONS, INC.
    Inventors: Anthony Reinberger, Paul Demone
  • Patent number: 8102164
    Abstract: Power factor correction converter control offset apparatus and methods are disclosed. In one aspect, an apparatus includes a control unit to generate a control signal to control a duty cycle of a PWM (Pulse Width Modulation) switching signal that controls a switch in a PFC (Power Factor Correction) converter. An offset unit is also included and is coupled to the control unit, to generate a variable offset signal to offset the control signal or a signal used by the control unit to generate the control signal.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: January 24, 2012
    Assignee: Power Integrations, Inc.
    Inventors: Roger Colbeck, Paul DeMone, Anthony Peter Ernest Reinberger
  • Publication number: 20120008426
    Abstract: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.
    Type: Application
    Filed: September 20, 2011
    Publication date: January 12, 2012
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventor: Paul DEMONE
  • Patent number: 8045413
    Abstract: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: October 25, 2011
    Assignee: Mosaid Technologies Incorporated
    Inventor: Paul Demone
  • Patent number: 8014172
    Abstract: A resonant mode power converter is controlled with a control unit including a feedback circuit coupled to generate a first current representative of an output of the power converter. A current limiting circuit is coupled to receive the first current and a second current generated in response to a reference voltage. The current limiting circuit is coupled to limit the first current in response to the second current. An oscillator is coupled to receive the first current to generate a control signal having a control frequency in response to the first current. An output voltage of the power converter is controlled in response to the control frequency of the control signal.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: September 6, 2011
    Assignee: Power Integrations, Inc.
    Inventors: Anthony Reinberger, Paul Demone
  • Patent number: 7957211
    Abstract: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: June 7, 2011
    Assignee: Mosaid Technologies Incorporation
    Inventor: Paul Demone
  • Publication number: 20110044074
    Abstract: A resonant mode power converter is controlled with a control unit including a feedback circuit coupled to generate a first current representative of an output of the power converter. A current limiting circuit is coupled to receive the first current and a second current generated in response to a reference voltage. The current limiting circuit is coupled to limit the first current in response to the second current. An oscillator is coupled to receive the first current to generate a control signal having a control frequency in response to the first current. An output voltage of the power converter is controlled in response to the control frequency of the control signal.
    Type: Application
    Filed: November 3, 2010
    Publication date: February 24, 2011
    Applicant: POWER INTEGRATIONS, INC.
    Inventors: Anthony Reinberger, Paul Demone
  • Publication number: 20100329051
    Abstract: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated
    Type: Application
    Filed: September 9, 2010
    Publication date: December 30, 2010
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventor: Paul DEMONE
  • Patent number: 7848117
    Abstract: The switching frequency of an LLC converter is controlled by a control unit to which a feedback circuit provides a first current dependent upon the output voltage of the converter. An oscillator circuit produces a sawtooth waveform at a frequency dependent upon the first current, up to a limit equal to a second current set by a resistor. Two complementary switch control signals are produced for controlling two switches of the converter for conduction in alternate cycles of the sawtooth waveform. A timer produces dead times between the two complementary switch control signals in dependence upon the second current. Another resistor provides a current constituting a minimum value of the first current, and a charging current of a capacitor in series with a resistor modifies the first current for soft starting of the converter.
    Type: Grant
    Filed: January 18, 2008
    Date of Patent: December 7, 2010
    Assignee: Power Integrations, Inc.
    Inventors: Anthony Reinberger, Paul Demone
  • Patent number: 7817484
    Abstract: A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising, a first delay circuit for delaying a word line timing pulse by a first predetermined period, a first logic circuit for logically combining the word line timing pulse and the delayed word line timing pulse to produce a sense amplifier enable signal, for enabling a sense amplifier power supply circuit, a second delay circuit for delaying the word line timing pulse by a second predetermined period, and a second logic circuit for logically combining the word line timing pulse and the second delayed word line timing pulse to produce a column select enable signal, for enabling selected ones of a plurality of column access devices wherein the second predetermined time period is selected so that ones of a plurality of column access devices are activated
    Type: Grant
    Filed: November 23, 2009
    Date of Patent: October 19, 2010
    Assignee: Mosaid Technologies Incorporated
    Inventor: Paul Demone
  • Publication number: 20100232237
    Abstract: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.
    Type: Application
    Filed: May 21, 2010
    Publication date: September 16, 2010
    Applicant: MOSAID TECHNOLOGIES INCORPORATED
    Inventor: Paul DEMONE
  • Patent number: 7751262
    Abstract: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: July 6, 2010
    Assignee: MOSAID Technologies Incorporated
    Inventor: Paul Demone