Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer above the substrate, a Schottky barrier material on the epitaxial layer, a Schottky metal contact extending into the Schottky barrier material, a fin structure that extends in a first direction, a first angled implant in a first side of the fin structure that has an orientation that is orthogonal to the first direction, and a second angled implant in a second side of the fin structure that has an orientation that is orthogonal to the first direction. The second side is opposite to the first side. A first cathode region and a second cathode region are coupled by parts of the first angled implant and the second angled implant that extend in the first direction.

Abstract: Transistor structures including a fin structure having multiple graded III-N material layers with polarization layers therebetween, integrated circuits including such transistor structures, and methods for forming the transistor structures are discussed. The transistor structures further include a source, a drain, and a gate coupled to the fin structure. The fin structure provides a multi-gate multi-nanowire confined transistor architecture.

Abstract: A transistor includes a polarization layer above a channel layer including a first III-Nitride (III-N) material, a gate electrode above the polarization layer, a source structure and a drain structure on opposite sides of the gate electrode, where the source structure and a drain structure each include a second III-N material. The transistor further includes a silicide on at least a portion of the source structure or the drain structure. A contact is coupled through the silicide to the source or drain structure.

Abstract: Integrated circuit architectures for load and input matching that include a capacitance selectable between a plurality of discrete levels, which are associated with a number of field effect transistors (FET) capacitor structures that are in an on-state. The capacitance comprises a metal-oxide-semiconductor (MOS) capacitance associated with each of the FET capacitor structures, and may be selectable through application of a bias voltage applied between a first circuit node and a second circuit node. Gate electrodes of the FET capacitor structures may be coupled in electrical parallel to the first circuit node, while source/drains of the FET capacitor structures are coupled in electrical parallel to the second circuit node. Where the FET capacitor structures have different gate-source threshold voltages, the number of FET capacitor structures in the on-state may be varied according to the bias voltage, and the capacitance correspondingly tuned to a desired value.

Abstract: A substrate contact diode is disclosed. The substrate contact includes a first type substrate implant tap in a substrate, a second type epitaxial implant in an epitaxial layer that is on the substrate, and a first type epitaxial region above the second type epitaxial implant. A contact electrode that extends upward from the top of the first type epitaxial region to the surface of an interlayer dielectric that surrounds the contact electrode.

Abstract: A diode is disclosed. The diode includes a semiconductor substrate, a hard mask formed above the substrate, vertically oriented components of a first material adjacent sides of the hard mask, and laterally oriented components of the first material on top of the hard mask. The laterally oriented components are oriented in a first direction and a second direction. The diode also includes a second material on top of the first material. The second material forms a Schottky barrier.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, an epitaxial layer on the substrate, a semiconductor interlayer on top of the epitaxial layer, a gate conductor above the semiconductor interlayer, a gate insulator on the bottom and sides of the gate conductor and contacting the top surface of the semiconductor interlayer, a source region extending into the epitaxial layer, and a drain region extending into the epitaxial layer. The semiconductor device also includes a first polarization layer on the semiconductor interlayer between the source region and the gate conductor and a second polarization layer on the semiconductor interlayer between the drain region and the gate conductor.

Abstract: Systems and methods for filtering data representative of consumers targeted for marketing campaigns that include receiving, at a first computer system operating on behalf of a payment card network, a first data set comprising pseudonymized data of a plurality of consumers derived from respective consumer files, the pseudonymized data of each consumer including a unique artificial identifier for the consumer, the first data set being received from a second, independent computer system storing keys configured to re-identify at least some of the pseudonymized data of the first data set; comparing, at the first computer system, the pseudonymized data of each of the consumers with payment card network criteria to generate a second data set comprising a subset of the first data set corresponding to a qualifying subset of the consumers and unique artificial identifiers included in the first data set; and transmitting the second data set from the first computer system to the second computer system.

Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate, a superlattice that includes a plurality of layers of alternating materials above the substrate, where each of the plurality of layers corresponds to a threshold voltage, a gate trench extending into the superlattice to a predetermined one of the plurality of layers of the superlattice structure, and a high-k layer on the bottom and sidewall of the trench, the high-k layer contacting an etch stop layer of one of the plurality of layers of alternating materials. A gate is located in the trench on top of the high-k layer.

Abstract: Field-effect transistors with buried gates and methods of manufacturing the same are disclosed. An example apparatus includes a source, a drain, and a semiconductor material positioned between the source and the drain. The example apparatus further includes a first gate positioned adjacent the semiconductor material. The example apparatus also includes a second gate positioned adjacent the semiconductor material. A portion of the semiconductor material is positioned between the first and second gates.

Abstract: An apparatus is provided which comprises: a substrate; one or more active devices adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

Abstract: Techniques are disclosed implementing acoustic wave resonator (AWR) filter architectures to enable integrated solutions requiring significantly less passive components. The primary AWR filter topology leverages the use of parallel resonator branches, each having a relatively narrow bandwidth that may be combined to form an overall broadband filter response. This architecture may be further modified using electronically-controlled switching components to dynamically turn specific branches on or off to tune the filter, thus realizing a programmable broadband solution. Shunt resonators may also be added to the AWR filter topology, which may also be controlled with the use of electronically-controlled switching components to provide further control with respect to roll-off and the location and number of notch frequencies.

Abstract: An apparatus is provided which comprises: a substrate; one or more active devices adjacent to the substrate; a first set of one or more layers to interconnect the one or more active devices; a second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Electrical test may be performed from front and back sides of a workpiece. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

Abstract: A semiconductor-on-insulator (SOI) substrate with a compliant substrate layer advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N devices (e.g., III-N HFETs) may be formed. The compliant layer may be (111) silicon, for example. The SOI substrate may further include another layer that may have one or more of lower electrical resistivity, greater thickness, or a different crystal orientation relative to the compliant substrate layer. A SOI substrate may include a (100) silicon layer advantageous for integrating Group IV devices (e.g., Si FETs), for example. To reduce parasitic coupling between an HFET and a substrate layer of relatively low electrical resistivity, one or more layers of the substrate may be removed within a region below the HFETs. Once removed, the resulting void may be backfilled with another material, or the void may be sealed, for example during back-end-of-line processing.

Abstract: Integrated circuit cell architectures including both front-side and back-side structures. One or more of back-side implant, semiconductor deposition, dielectric deposition, metallization, film patterning, and wafer-level layer transfer is integrated with front-side processing. Such double-side processing may entail revealing a back side of structures fabricated from the front-side of a substrate. Host-donor substrate assemblies may be built-up to support and protect front-side structures during back-side processing. Front-side devices, such as FETs, may be modified and/or interconnected during back-side processing. Back-side devices, such as FETs, may be integrated with front-side devices to expand device functionality, improve performance, or increase device density.

Abstract: A structure, comprising an island comprising a III-N material. The island extends over a substrate and has a sloped sidewall. A cap comprising a III-N material extends laterally from a top surface and overhangs the sidewall of the island. A device, such as a transistor, light emitting diode, or resonator, may be formed within, or over, the cap.

Abstract: Field-effect transistors with buried gates and methods of manufacturing the same are disclosed. An example apparatus includes a source, a drain, and a semiconductor material positioned between the source and the drain. The example apparatus further includes a first gate positioned adjacent the semiconductor material. The example apparatus also includes a second gate positioned adjacent the semiconductor material. A portion of the semiconductor material is positioned between the first and second gates.

Abstract: An apparatus is provided which comprises: a substrate; a first active device adjacent to the substrate; a first set of one or more layers to interconnect with the first active device; a second set of one or more layers; a second active and/or passive device coupled to the second set of one or more layers; and a layer adjacent to one of the layers of the first and second sets, wherein the layer is to bond the one of the layers of the first and second sets.

Abstract: An integrated circuit structure and methodologies of forming same. In an embodiment, the integrated circuit structure includes a transistor gate structure in a first region of semiconductor material and a diode in a second region of the semiconductor material. The gate structure has a gate electrode of conductive material with a liner along sides and a bottom of the gate electrode. The gate electrode has a gate length less than a threshold dimension value. The diode includes a body of the conductive material in contact with the semiconductor material and includes the liner along sides of the body of conductive material. The body of conductive material has a lateral dimension greater than the threshold dimension value. The liner can include, for example, a gate dielectric and a diffusion barrier in some embodiments. In other embodiments, the liner is the gate dielectric (without any diffusion barrier).