Abstract: The invention is composition and methods that restore balance to the stress-related steroidal hormone cascade. Upon co-administration, the compounds of the invention restore balance to the cascade and promote or restore normal function in patients suffering from a disorder having a primary psychological stress component. The compositions include a selected combination of isoflavones, alpha lipoic acid, and L dopamine or a precursor thereof, and are preferably obtained from the natural sources disclosed herein. The uses of the invention include administration of the disclosed compositions to patients suffering from PTSD, fibromyalgia, endometriosis, and other disorders having a common chronic stress component.

Abstract: The invention is composition and methods that restore balance to the stress-related steroidal hormone cascade. Upon co-administration, the compounds of the invention restore balance to the cascade and promote or restore normal function in patients suffering from a disorder having a primary psychological stress component. The compositions include a selected combination of isoflavones, alpha lipoic acid, and L dopamine or a precursor thereof, and are preferably obtained from the natural sources disclosed herein. The uses of the invention include administration of the disclosed compositions to patients suffering from PTSD, fibromyalgia, endometriosis, and other disorders having a common chronic stress component.

Abstract: The invention is composition and methods that restore balance to the stress-related steroidal hormone cascade. Upon co-administration, the compounds of the invention restore balance to the cascade and promote or restore normal function in patients suffering from a disorder having a primary psychological stress component. The compositions include a selected combination of isoflavones, alpha lipoic acid, and L dopamine or a precursor thereof, and are preferably obtained from the natural sources disclosed herein. The uses of the invention include administration of the disclosed compositions to patients suffering from PTSD, fibromyalgia, endometriosis, and other disorders having a common chronic stress component.

Abstract: The invention is composition and methods that restore balance to the stress-related steroidal hormone cascade. Upon co-administration, the compounds of the invention restore balance to the cascade and promote or restore normal function in patients suffering from a disorder having a primary psychological stress component. The compositions include a selected combination of isoflavones, alpha lipoic acid, and L dopamine or a precursor thereof, and are preferably obtained from the natural sources disclosed herein. The uses of the invention include administration of the disclosed compositions to patients suffering from PTSD, fibromyalgia, endometriosis, and other disorders having a common chronic stress component.

Abstract: The invention is composition and methods that restore balance to the stress-related steroidal hormone cascade. Upon co-administration, the compounds of the invention restore balance to the cascade and promote or restore normal function in patients suffering from a disorder having a primary psychological stress component. The compositions include a selected combination of isoflavones, alpha lipoic acid, and L dopamine or a precursor thereof, and are preferably obtained from the natural sources disclosed herein. The uses of the invention include administration of the disclosed compositions to patients suffering from PTSD, fibromyalgia, endometriosis, and other disorders having a common chronic stress component.

Abstract: A CPU having a cluster VLIW architecture is shown which operates in both a high instruction level parallelism (ILP) mode and a low ILP mode. In high ILP mode, the CPU executes wide instruction words using all operational clusters of the CPU and all of a main instruction cache and main data cache of the CPU are accessible to a high ILP task. The CPU also includes a mini-instruction cache, a mini-instruction register and a mini-data cache which are inactive during high ILP mode. An instruction level controller in the CPU receives a low ILP signal, such as an interrupt or function call to a low ILP routine, and switches to low ILP mode. In low ILP mode, the main instruction cache and main data cache are deactivated to preserve their contents. At the same time, a predetermined cluster remains active while the remaining clusters are also deactivated. The low ILP task executes instructions from the mini-instruction cache which are input to the predetermined cluster through the mini-instruction register.

Abstract: A translation look-aside buffer (TLB) for translating a variable page size virtual page number to a physical page number. The TLB partitions the virtual page number into an upper portion and a lower portion. The upper portion is always compared to an upper virtual page number entry in a first content addressable memory while only certain bits of lower portion are selectively compared to a corresponding number of bits in a lower virtual page number entry in a second content addressable memory. The number of bits compared in the second content addressable memory is determined by the specified size of the physical page. The TLB includes a page size memory having a plurality of page size entries wherein the certain number of bits for each of the lower virtual page entries is specified by a corresponding page size entry. Associated with each bit in the lower virtual page number entries is an enable transistor for selectively enabling the comparison of that bit in the lower virtual page number entry.

Abstract: A cache memory system with a secondary cache integrated with a direct mapped primary cache in a single structure preferably constructed on a VLSI chip. The secondary cache uses the same output data bitlines, sense amplifiers, and bus drivers as the direct mapped cache. In a first machine cycle, input address tags are simultaneously compared to tag bits in the primary cache and the secondary cache. If the comparison results in a miss in the primary cache and a hit in the secondary cache, the secondary cache data is fed to the microprocessor in the next machine cycle, precluding the need for a main memory access. Thus, allowing data to be read directly from the secondary cache without using an extra machine cycle to load it first into the direct cache. The secondary cache comprises a miss cache which is loaded from main memory with data missing from the primary cache in the first machine cycle.

Abstract: An improved memory type multi-ported data storage device is disclosed. The storage device operates to overcome the cell stability problems associated with the prior art by unidirectionally isolating memory cells of the multi-ported data storage device from read ports of the multi-ported data storage device. The unidirectional isolation operates to prevent external signals from the read ports and read port loading from influencing data stored in the memory cells, but continues to allow the memory cells to be read by the read ports associated therewith. The improved multi-ported data storage device not only allows simultaneous access to its memory cells by a large number of read ports without fear that cell stability will cause corruption of the memory cells, but also requires only a minimal amount of additional die area. Moreover, access time is independent of the number of ports being simultaneously accessed.

Abstract: A scalable register file including first and second micro-register files organized in a pipelined fashion to minimize the access time of the register file where there are a large number of registers or multiple functional units. Interposed between the first and second micro-register files are a first plurality of pipeline registers for storing the register contents fetched from the first micro-register file during a first pipeline cycle. A second plurality of pipeline registers are coupled to the second micro-register files for storing the register contents fetched from the second micro-register file during a second pipeline stage and those registers being stored in the first plurality of pipeline registers. The first plurality of pipeline registers are coupled to the bit lines of the second micro-register file.