Patents by Inventor Paul H. Wermer

Paul H. Wermer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7535728
    Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: May 19, 2009
    Assignee: Intel Corporation
    Inventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
  • Patent number: 7348496
    Abstract: Embodiments of the present invention include forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate, using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as an organic polymer or an organic polymer mixture. Embodiments of the present invention also include forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and providing an embedded capacitor to reduce loop inductance.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventors: Paul H. Wermer, Brian Kaiser
  • Patent number: 7159313
    Abstract: To decrease the thickness, or stack height, of an electronics package, the package includes a solderless compression connector between an integrated circuit (IC) package and a substrate such as a printed circuit board (PCB). In one embodiment, the IC package is mounted on the substrate using a land grid array arrangement. Corresponding lands on the IC package and substrate are coupled using a solderless compression connector. The compression connector includes a plurality of electrically conductive particles, and a thin, flexible apertured support that aligns the particles with corresponding lands on the IC package and substrate. A compression connector may also be used to electrically couple an IC to an IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system, are also described.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: January 9, 2007
    Assignee: Intel Corporation
    Inventors: Ajit V. Sathe, Paul H. Wermer
  • Patent number: 7136275
    Abstract: The present invention includes a dielectric. The dielectric includes a polymer that has a high dielectric constant. The polymer includes polarizable species. The present invention also includes an embedded capacitor, and an IC package made with the dielectric.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: November 14, 2006
    Assignee: Intel Corporation
    Inventors: Paul A. Koning, Paul H. Wermer
  • Patent number: 7120031
    Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: October 10, 2006
    Assignee: Intel Corporation
    Inventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
  • Patent number: 7067356
    Abstract: A microelectronic device fabrication technology that places at least one microelectronic die within at least one opening in a microelectronic package core and secures the microelectronic die/dice within the opening(s) with an encapsulation material, that encapsulates at least one microelectronic die within an encapsulation material without a microelectronic package core, or that secures at least one microelectronic die within at least one opening in a heat spreader. A laminated interconnector of dielectric materials and conductive traces is then attached to the microelectronic die/dice and at least one of following: the encapsulation material, the microelectronic package core, and the heat spreader, to form a microelectronic device.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: June 27, 2006
    Assignee: Intel Corporation
    Inventors: Steven Towle, Paul H. Wermer
  • Patent number: 6840777
    Abstract: To decrease the thickness, or stack height, of an electronics package, the package includes a solderless compression connector between an integrated circuit (IC) package and a substrate such as a printed circuit board (PCB). In one embodiment, the IC package is mounted on the substrate using a land grid array arrangement. Corresponding lands on the IC package and substrate are coupled using a solderless compression connector. The compression connector includes a plurality of electrically conductive elements, such as compressible button contacts, and an apertured support that aligns the button contacts with corresponding lands on the IC package and substrate. In another embodiment, the connector includes electrically conductive pins embedded in a thin plastic sheet. In a further embodiment, the connector includes a microcrystalline film having electrically conductive crystals. In a further embodiment, the compression connector is used within an IC package to couple an IC to an IC package substrate.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: January 11, 2005
    Assignee: Intel Corporation
    Inventors: Ajit V. Sathe, Paul H. Wermer
  • Patent number: 6829133
    Abstract: Embodiments of the present invention include forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as an organic polymer or an organic polymer mixture. Embodiments of the present invention also include forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and providing an embedded capacitor to reduce loop inductance.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: December 7, 2004
    Assignee: Intel Corporation
    Inventors: Paul H. Wermer, Brian Kaiser
  • Publication number: 20040238942
    Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.
    Type: Application
    Filed: July 2, 2004
    Publication date: December 2, 2004
    Applicant: Intel Corporation
    Inventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
  • Patent number: 6775150
    Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.
    Type: Grant
    Filed: August 30, 2000
    Date of Patent: August 10, 2004
    Assignee: Intel Corporation
    Inventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
  • Publication number: 20030227077
    Abstract: A microelectronic device fabrication technology that places at least one microelectronic die within at least one opening in a microelectronic package core and secures the microelectronic die/dice within the opening(s) with an encapsulation material, that encapsulates at least one microelectronic die within an encapsulation material without a microelectronic package core, or that secures at least one microelectronic die within at least one opening in a heat spreader. A laminated interconnector of dielectric materials and conductive traces is then attached to the microelectronic die/dice and at least one of following: the encapsulation material, the microelectronic package core, and the heat spreader, to form a microelectronic device.
    Type: Application
    Filed: April 28, 2003
    Publication date: December 11, 2003
    Applicant: Intel Corporation
    Inventors: Steven Towle, Paul H. Wermer
  • Publication number: 20030205406
    Abstract: The present invention includes forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as organic polymers and organic polymer mixtures. The present invention also includes forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and an embedded capacitor to reduce loop inductance.
    Type: Application
    Filed: April 21, 2003
    Publication date: November 6, 2003
    Applicant: Intel Corporation
    Inventors: Paul H. Wermer, Brian Kaiser
  • Patent number: 6605551
    Abstract: Embodiments of the present invention include forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate, using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as an organic polymer or an organic polymer mixture. Embodiments of the present invention also include forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and providing an embedded capacitor to reduce loop inductance.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: August 12, 2003
    Assignee: Intel Corporation
    Inventors: Paul H. Wermer, Brian Kaiser
  • Patent number: 6555906
    Abstract: A microelectronic device fabrication technology that places at least one microelectronic die within at least one opening in a microelectronic package core and secures the microelectronic die/dice within the opening(s) with an encapsulation material, that encapsulates at least one microelectronic die within an encapsulation material without a microelectronic package core, or that secures at least one microelectronic die within at least one opening in a heat spreader. A laminated interconnector of dielectric materials and conductive traces is then attached to the microelectronic die/dice and at least one of following: the encapsulation material, the microelectronic package core, and the heat spreader, to form a microelectronic device.
    Type: Grant
    Filed: December 15, 2000
    Date of Patent: April 29, 2003
    Assignee: Intel Corporation
    Inventors: Steven Towle, Paul H. Wermer
  • Publication number: 20030011960
    Abstract: The present invention includes a dielectric. The dielectric comprises a polymer that has a high dielectric constant. The polymer comprises polarizable species. The present invention also includes an embedded capacitor, and an IC package made with the dielectric.
    Type: Application
    Filed: September 12, 2002
    Publication date: January 16, 2003
    Applicant: Intel Corporation
    Inventors: Paul A. Koning, Paul H. Wermer
  • Patent number: 6480370
    Abstract: The present invention includes a dielectric. The dielectric comprises a polymer that has a high dielectric constant. The polymer comprises polarizable species. The present invention also includes an embedded capacitor, and an IC package made with the dielectric.
    Type: Grant
    Filed: December 28, 1999
    Date of Patent: November 12, 2002
    Assignee: Intel Corporation
    Inventors: Paul A. Koning, Paul H. Wermer
  • Publication number: 20020105774
    Abstract: The present invention includes forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as organic polymers and organic polymer mixtures. The present invention also includes forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and an embedded capacitor to reduce loop inductance.
    Type: Application
    Filed: December 8, 2000
    Publication date: August 8, 2002
    Applicant: Intel Corporation
    Inventors: Paul H. Wermer, Brian Kaiser
  • Publication number: 20020074641
    Abstract: A microelectronic device fabrication technology that places at least one microelectronic die within at least one opening in a microelectronic package core and secures the microelectronic die/dice within the opening(s) with an encapsulation material, that encapsulates at least one microelectronic die within an encapsulation material without a microelectronic package core, or that secures at least one microelectronic die within at least one opening in a heat spreader. A laminated interconnector of dielectric materials and conductive traces is then attached to the microelectronic die/dice and at least one of following: the encapsulation material, the microelectronic package core, and the heat spreader, to form a microelectronic device.
    Type: Application
    Filed: December 15, 2000
    Publication date: June 20, 2002
    Inventors: Steven Towle, Paul H. Wermer
  • Publication number: 20020065965
    Abstract: To decrease the thickness, or stack height, of an electronics package, the package includes a solderless compression connector between an integrated circuit (IC) package and a substrate such as a printed circuit board (PCB). In one embodiment, the IC package is mounted on the substrate using a land grid array arrangement. Corresponding lands on the IC package and substrate are coupled using a solderless compression connector. The compression connector includes a plurality of electrically conductive elements, such as compressible button contacts, and an apertured support that aligns the button contacts with corresponding lands on the IC package and substrate. In another embodiment, the connector includes electrically conductive pins embedded in a thin plastic sheet. In a further embodiment, the connector includes a microcrystalline film having electrically conductive crystals. In a further embodiment, the compression connector is used within an IC package to couple an IC to an IC package substrate.
    Type: Application
    Filed: November 30, 2000
    Publication date: May 30, 2002
    Applicant: Intel Corporation
    Inventors: Ajit V. Sathe, Paul H. Wermer