Patents by Inventor Paul H. Wermer
Paul H. Wermer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7535728Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.Type: GrantFiled: August 22, 2006Date of Patent: May 19, 2009Assignee: Intel CorporationInventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
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Patent number: 7348496Abstract: Embodiments of the present invention include forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate, using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as an organic polymer or an organic polymer mixture. Embodiments of the present invention also include forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and providing an embedded capacitor to reduce loop inductance.Type: GrantFiled: December 3, 2004Date of Patent: March 25, 2008Assignee: Intel CorporationInventors: Paul H. Wermer, Brian Kaiser
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Patent number: 7159313Abstract: To decrease the thickness, or stack height, of an electronics package, the package includes a solderless compression connector between an integrated circuit (IC) package and a substrate such as a printed circuit board (PCB). In one embodiment, the IC package is mounted on the substrate using a land grid array arrangement. Corresponding lands on the IC package and substrate are coupled using a solderless compression connector. The compression connector includes a plurality of electrically conductive particles, and a thin, flexible apertured support that aligns the particles with corresponding lands on the IC package and substrate. A compression connector may also be used to electrically couple an IC to an IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly, an electronic system, and a data processing system, are also described.Type: GrantFiled: November 30, 2004Date of Patent: January 9, 2007Assignee: Intel CorporationInventors: Ajit V. Sathe, Paul H. Wermer
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Patent number: 7136275Abstract: The present invention includes a dielectric. The dielectric includes a polymer that has a high dielectric constant. The polymer includes polarizable species. The present invention also includes an embedded capacitor, and an IC package made with the dielectric.Type: GrantFiled: September 12, 2002Date of Patent: November 14, 2006Assignee: Intel CorporationInventors: Paul A. Koning, Paul H. Wermer
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Patent number: 7120031Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.Type: GrantFiled: July 2, 2004Date of Patent: October 10, 2006Assignee: Intel CorporationInventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
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Patent number: 7067356Abstract: A microelectronic device fabrication technology that places at least one microelectronic die within at least one opening in a microelectronic package core and secures the microelectronic die/dice within the opening(s) with an encapsulation material, that encapsulates at least one microelectronic die within an encapsulation material without a microelectronic package core, or that secures at least one microelectronic die within at least one opening in a heat spreader. A laminated interconnector of dielectric materials and conductive traces is then attached to the microelectronic die/dice and at least one of following: the encapsulation material, the microelectronic package core, and the heat spreader, to form a microelectronic device.Type: GrantFiled: April 28, 2003Date of Patent: June 27, 2006Assignee: Intel CorporationInventors: Steven Towle, Paul H. Wermer
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Patent number: 6840777Abstract: To decrease the thickness, or stack height, of an electronics package, the package includes a solderless compression connector between an integrated circuit (IC) package and a substrate such as a printed circuit board (PCB). In one embodiment, the IC package is mounted on the substrate using a land grid array arrangement. Corresponding lands on the IC package and substrate are coupled using a solderless compression connector. The compression connector includes a plurality of electrically conductive elements, such as compressible button contacts, and an apertured support that aligns the button contacts with corresponding lands on the IC package and substrate. In another embodiment, the connector includes electrically conductive pins embedded in a thin plastic sheet. In a further embodiment, the connector includes a microcrystalline film having electrically conductive crystals. In a further embodiment, the compression connector is used within an IC package to couple an IC to an IC package substrate.Type: GrantFiled: November 30, 2000Date of Patent: January 11, 2005Assignee: Intel CorporationInventors: Ajit V. Sathe, Paul H. Wermer
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Patent number: 6829133Abstract: Embodiments of the present invention include forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as an organic polymer or an organic polymer mixture. Embodiments of the present invention also include forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and providing an embedded capacitor to reduce loop inductance.Type: GrantFiled: April 21, 2003Date of Patent: December 7, 2004Assignee: Intel CorporationInventors: Paul H. Wermer, Brian Kaiser
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Publication number: 20040238942Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.Type: ApplicationFiled: July 2, 2004Publication date: December 2, 2004Applicant: Intel CorporationInventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
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Patent number: 6775150Abstract: To reduce switching noise, the power supply terminals of an integrated circuit die are coupled to the respective terminals of at least one embedded capacitor in a multilayer ceramic/organic hybrid substrate. In one embodiment, a ceramic portion of the substrate includes at least one capacitor formed of a high permittivity layer sandwiched between conductive planes. An organic portion of the substrate includes suitable routing and fan-out of power and signal conductors. The organic portion includes a build-up of multiple layers of organic material overlying the ceramic portion. Also described are an electronic system, a data processing system, and various methods of manufacture.Type: GrantFiled: August 30, 2000Date of Patent: August 10, 2004Assignee: Intel CorporationInventors: Kishore K. Chakravorty, Paul H. Wermer, David G. Figueroa, Debabrata Gupta
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Publication number: 20030227077Abstract: A microelectronic device fabrication technology that places at least one microelectronic die within at least one opening in a microelectronic package core and secures the microelectronic die/dice within the opening(s) with an encapsulation material, that encapsulates at least one microelectronic die within an encapsulation material without a microelectronic package core, or that secures at least one microelectronic die within at least one opening in a heat spreader. A laminated interconnector of dielectric materials and conductive traces is then attached to the microelectronic die/dice and at least one of following: the encapsulation material, the microelectronic package core, and the heat spreader, to form a microelectronic device.Type: ApplicationFiled: April 28, 2003Publication date: December 11, 2003Applicant: Intel CorporationInventors: Steven Towle, Paul H. Wermer
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Publication number: 20030205406Abstract: The present invention includes forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as organic polymers and organic polymer mixtures. The present invention also includes forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and an embedded capacitor to reduce loop inductance.Type: ApplicationFiled: April 21, 2003Publication date: November 6, 2003Applicant: Intel CorporationInventors: Paul H. Wermer, Brian Kaiser
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Patent number: 6605551Abstract: Embodiments of the present invention include forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate, using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as an organic polymer or an organic polymer mixture. Embodiments of the present invention also include forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and providing an embedded capacitor to reduce loop inductance.Type: GrantFiled: December 8, 2000Date of Patent: August 12, 2003Assignee: Intel CorporationInventors: Paul H. Wermer, Brian Kaiser
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Patent number: 6555906Abstract: A microelectronic device fabrication technology that places at least one microelectronic die within at least one opening in a microelectronic package core and secures the microelectronic die/dice within the opening(s) with an encapsulation material, that encapsulates at least one microelectronic die within an encapsulation material without a microelectronic package core, or that secures at least one microelectronic die within at least one opening in a heat spreader. A laminated interconnector of dielectric materials and conductive traces is then attached to the microelectronic die/dice and at least one of following: the encapsulation material, the microelectronic package core, and the heat spreader, to form a microelectronic device.Type: GrantFiled: December 15, 2000Date of Patent: April 29, 2003Assignee: Intel CorporationInventors: Steven Towle, Paul H. Wermer
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Publication number: 20030011960Abstract: The present invention includes a dielectric. The dielectric comprises a polymer that has a high dielectric constant. The polymer comprises polarizable species. The present invention also includes an embedded capacitor, and an IC package made with the dielectric.Type: ApplicationFiled: September 12, 2002Publication date: January 16, 2003Applicant: Intel CorporationInventors: Paul A. Koning, Paul H. Wermer
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Patent number: 6480370Abstract: The present invention includes a dielectric. The dielectric comprises a polymer that has a high dielectric constant. The polymer comprises polarizable species. The present invention also includes an embedded capacitor, and an IC package made with the dielectric.Type: GrantFiled: December 28, 1999Date of Patent: November 12, 2002Assignee: Intel CorporationInventors: Paul A. Koning, Paul H. Wermer
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Publication number: 20020105774Abstract: The present invention includes forming a thin, conformal, high-integrity dielectric coating between conductive layers in a via-in-via structure in an organic substrate using an electrocoating process to reduce loop inductance between the conductive layers. The dielectric coating is formed using a high dielectric constant material such as organic polymers and organic polymer mixtures. The present invention also includes forming a thin, dielectric coating between conductive layers on a substantially planar substrate material and an embedded capacitor to reduce loop inductance.Type: ApplicationFiled: December 8, 2000Publication date: August 8, 2002Applicant: Intel CorporationInventors: Paul H. Wermer, Brian Kaiser
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Publication number: 20020074641Abstract: A microelectronic device fabrication technology that places at least one microelectronic die within at least one opening in a microelectronic package core and secures the microelectronic die/dice within the opening(s) with an encapsulation material, that encapsulates at least one microelectronic die within an encapsulation material without a microelectronic package core, or that secures at least one microelectronic die within at least one opening in a heat spreader. A laminated interconnector of dielectric materials and conductive traces is then attached to the microelectronic die/dice and at least one of following: the encapsulation material, the microelectronic package core, and the heat spreader, to form a microelectronic device.Type: ApplicationFiled: December 15, 2000Publication date: June 20, 2002Inventors: Steven Towle, Paul H. Wermer
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Publication number: 20020065965Abstract: To decrease the thickness, or stack height, of an electronics package, the package includes a solderless compression connector between an integrated circuit (IC) package and a substrate such as a printed circuit board (PCB). In one embodiment, the IC package is mounted on the substrate using a land grid array arrangement. Corresponding lands on the IC package and substrate are coupled using a solderless compression connector. The compression connector includes a plurality of electrically conductive elements, such as compressible button contacts, and an apertured support that aligns the button contacts with corresponding lands on the IC package and substrate. In another embodiment, the connector includes electrically conductive pins embedded in a thin plastic sheet. In a further embodiment, the connector includes a microcrystalline film having electrically conductive crystals. In a further embodiment, the compression connector is used within an IC package to couple an IC to an IC package substrate.Type: ApplicationFiled: November 30, 2000Publication date: May 30, 2002Applicant: Intel CorporationInventors: Ajit V. Sathe, Paul H. Wermer