Abstract: A computer program operable to interface with a browser and access a navigation device to utilize navigation information. The computer program may acquire information from the navigation device and provide the acquired information to the browser. The computer program may also acquire navigation information from the browser and provide the acquired information to the navigation device.

Abstract: A circuit and method for increasing the output data per unit time from a computer to its associated peripheral terminals or utilization devices is disclosed in which the computer output address and data lines are time multiplexed by a novel decoding technique which enables the address bits and data bits to be interpreted together to form a new data word having a number of bits equal to the sum of the original data bits and the address bits interpreted as data bits. A plurality of decoders, each at a peripheral terminal and each having an identification address code, enable a window for decoding multiple transfers of data on output address and data lines, said window having a predetermined time duration during which all other peripheral identification address codes are locked out, until the data transfer is completed.A microprocessor embodying the invention is also disclosed in which the output data capability is increased from eight to sixteen bits without hardware modification to the microprocessor.

Abstract: A system and method is disclosed wherein a microprocessor having an eight-bit data bus and a sixteen-bit address bus is interconnected with a peripheral device to which a certain amount of data must be transferred at a data rate greater than is possible by utilizing the eight-bit data bus to accomplish the transfer. The system includes a microprocessor, a memory, and a peripheral device interconnected by the eight-bit data bus, the sixteen-bit address bus and a read-write conductor. The peripheral device includes an address code recognition circuit coupled to the data bus and one of the address lines, and also includes a fifteen-bit buffer connected to fifteen lines of the address bus. The address code recognition circuit generates an output which is gated with the read-write conductor to generate a clock signal which enables the data on the address bus to be loaded into the fifteen-bit buffer, from which it may be utilized by the peripheral device.