Patents by Inventor Paul J. Griffith

Paul J. Griffith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220088392
    Abstract: A new architecture is disclosed for an IPG having a master and slave electrode driver integrated circuits (ICs). The electrode outputs on the ICs are wired together. Each IC can be programmed to provide pulses with different frequencies. Active timing channels in master and slave ICs are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other IC so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.
    Type: Application
    Filed: December 2, 2021
    Publication date: March 24, 2022
    Inventors: Emanuel Feldman, Jordi Parramon, Paul J. Griffith, Jess Shi, Robert Tong, Goran Marnfeldt
  • Patent number: 11207521
    Abstract: A new architecture is disclosed for an IPG having a master and slave electrode driver integrated circuits (ICs). The electrode outputs on the ICs are wired together. Each IC can be programmed to provide pulses with different frequencies. Active timing channels in master and slave ICs are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other IC so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: December 28, 2021
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventors: Emanuel Feldman, Jordi Parramon, Paul J. Griffith, Jess Shi, Robert Tong, Goran Marnfeldt
  • Publication number: 20200316381
    Abstract: A current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG) is disclosed. Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide coarse and fine current resolutions to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).
    Type: Application
    Filed: June 17, 2020
    Publication date: October 8, 2020
    Inventors: Jordi Parramon, David K.L. Peterson, Paul J. Griffith
  • Patent number: 10744325
    Abstract: A current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG) is disclosed. Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide coarse and fine current resolutions to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: August 18, 2020
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventors: Jordi Parramon, David K. L. Peterson, Paul J. Griffith
  • Publication number: 20190299007
    Abstract: A new architecture is disclosed for an IPG having a master and slave electrode driver integrated circuits (ICs). The electrode outputs on the ICs are wired together. Each IC can be programmed to provide pulses with different frequencies. Active timing channels in master and slave ICs are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other IC so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.
    Type: Application
    Filed: June 17, 2019
    Publication date: October 3, 2019
    Inventors: Emanuel Feldman, Jordi Parramon, Paul J. Griffith, Jess Shi, Robert Tong, Goran Marnfeldt
  • Patent number: 10391322
    Abstract: Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: August 27, 2019
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventors: Paul J. Griffith, Goran N. Marnfeldt, Jordi Parramon
  • Patent number: 10363422
    Abstract: Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: July 30, 2019
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventors: Emanuel Feldman, Jordi Parramon, Paul J. Griffith, Jess Shi, Robert Tong, Goran Marnfeldt
  • Publication number: 20180178012
    Abstract: A current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG) is disclosed. Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide coarse and fine current resolutions to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Inventors: Jordi Parramon, David K.L. Peterson, Paul J. Griffith
  • Publication number: 20180169424
    Abstract: Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.
    Type: Application
    Filed: February 14, 2018
    Publication date: June 21, 2018
    Inventors: Paul J. Griffith, Goran N. Marnfeldt, Jordi Parramon
  • Patent number: 9956411
    Abstract: A current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG) is disclosed. Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide coarse and fine current resolutions to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: May 1, 2018
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventors: Jordi Parramon, David K. L. Peterson, Paul J. Griffith
  • Patent number: 9925385
    Abstract: Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: March 27, 2018
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventors: Paul J. Griffith, Goran N. Marnfeldt, Jordi Parramon
  • Patent number: 9795793
    Abstract: Architectures for an implantable neurostimulator system having a plurality of electrode-driver integrated circuits (ICs) in provided. Electrodes from either or both ICs can be chosen to provide stimulation, and one of the IC acts as the master while the other acts as the slave. A parallel bus operating in accordance with a communication protocol couples the ICs, and certain functional blocks not needed in the slave are disabled. Stimulation parameters are loaded via the bus into each IC, and a stimulation enable command is issued on the bus to ensure simultaneous stimulation from the electrodes on both ICs. Clocking strategies are also disclosed to allow clocking of the master and slave ICs to be independently controlled, and to ensure that relevant internal and bus clocks used in the system are synchronized.
    Type: Grant
    Filed: October 5, 2011
    Date of Patent: October 24, 2017
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventors: Jordi Parramon, Emanuel Feldman, Paul J. Griffith, Jess W. Shi
  • Publication number: 20170216600
    Abstract: Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.
    Type: Application
    Filed: April 19, 2017
    Publication date: August 3, 2017
    Inventors: Emanuel Feldman, Jordi Parramon, Paul J. Griffith, Jess Shi, Robert Tong, Goran Marnfeldt
  • Patent number: 9656081
    Abstract: Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: May 23, 2017
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventors: Emanuel Feldman, Jordi Parramon, Paul J. Griffith, Jess Shi, Robert Tong, Goran Marnfeldt
  • Publication number: 20170021181
    Abstract: Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.
    Type: Application
    Filed: October 10, 2016
    Publication date: January 26, 2017
    Inventors: Paul J. Griffith, Goran N. Marnfeldt, Jordi Parramon
  • Patent number: 9468771
    Abstract: Timing channel circuitry for controlling stimulation circuitry in an implantable stimulator is disclosed. The timing channel circuitry comprises a addressable memory. Data for the various phases of a desired pulse are stored in the memory using different numbers of words, including a command indicative of the number of words in the phase, a next address for the next phase stored in the memory, and a pulse width or duration of the current phase, control data for the stimulation circuitry, pulse amplitude, and electrode data. The command data is used to address through the words in the current phase via the address bus, which words are sent to a control register for the stimulation circuitry. After the duration of the pulse width for the current phase has passed, the stored next address is used to access the data for the next phase stored in the memory.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: October 18, 2016
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventors: Paul J. Griffith, Goran N. Marnfeldt, Jordi Parramon
  • Publication number: 20160213929
    Abstract: A current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG) is disclosed. Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide coarse and fine current resolutions to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).
    Type: Application
    Filed: April 6, 2016
    Publication date: July 28, 2016
    Inventors: Jordi Parramon, David K.L. Peterson, Paul J. Griffith
  • Publication number: 20160184591
    Abstract: Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.
    Type: Application
    Filed: March 7, 2016
    Publication date: June 30, 2016
    Inventors: Emanuel Feldman, Jordi Parramon, Paul J. Griffith, Jess Shi, Robert Tong, Goran Marnfeldt
  • Patent number: 9308371
    Abstract: A current generation architecture for an implantable stimulator device such as an Implantable Pulse Generator (IPG) is disclosed. Current source and sink circuitry are both divided into coarse and fine portions, which respectively can provide coarse and fine current resolutions to a specified electrode on the IPG. The coarse portion is distributed across all of the electrodes and so can source or sink current to any of the electrodes. The coarse portion is divided into a plurality of stages, each of which is capable via an associated switch bank of sourcing or sinking a coarse amount of current to or from any one of the electrodes on the device. The fine portion of the current generation circuit preferably includes source and sink circuitry dedicated to each of the electrode on the device, which can comprise digital-to-analog current converters (DACs).
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: April 12, 2016
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventors: Jordi Parramon, David K. L. Peterson, Paul J. Griffith
  • Publication number: 20160082260
    Abstract: An improved architecture for an implantable medical device such as an implantable pulse generator (IPG) is disclosed. In one embodiment, the various functional blocks for the IPG are incorporated into a signal integrated circuit (IC). Each of the functional blocks communicates with each other, and with other off-chip devices if necessary, via a centralized bus governed by a communication protocol. To communicate with the bus and to adhere to the protocol, each circuit block includes bus interface circuitry adherent with that protocol. Because each block complies with the protocol, any given block can easily be modified or upgraded without affecting the design of the other blocks, facilitating debugging and upgrading of the IPG circuitry. Moreover, because the centralized bus can be taken off the integrated circuit, extra circuitry can easily be added off chip to modify or add functionality to the IPG.
    Type: Application
    Filed: December 7, 2015
    Publication date: March 24, 2016
    Inventors: Paul J. Griffith, Jordi Parramon, Goran Marnfeldt, Daniel Aghassian, Kiran Nimmagadda, Emanuel Feldman, Jess W. Shi